JP2008159976A - Silicon epitaxial wafer, method of manufacturing the same, method of manufacturing semiconductor device, and method of manufacturing soi wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon epitaxial wafer which has high gettering capability and is capable of reducing the total cost of semiconductor device fabrication, by facilitating film thickness control in each device process to be carried out readily and enabling the process of thinning the silicon substrate, after finishing the device fabrication to be carried out readily. <P>SOLUTION: The silicon epitaxial wafer includes at least a strained SiGe layer on a silicon substrate, a Si-protecting layer on the strained SiGe layer, and an epitaxial Si layer on the Si-protecting layer, wherein a heavily-doped Si layer is provided, at least in between the silicon substrate and the strained SiGe layer, or in between the Si protection layer and the epitaxial Si layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high gettering silicon epitaxial wafer used for a MOS device, a manufacturing method thereof, a manufacturing method of a semiconductor device using the same, and a manufacturing method of an SOI wafer.

Silicon epitaxial wafers for MOS devices have been increasing in diameter year by year, and 300 mm wafers are now mainstream. Increasingly, there are increasing demands for (1) completeness of device formation regions, (2) high gettering capability, and (3) cost reduction. Conventionally, from the viewpoint of latch-up resistance and gettering capability, a low concentration (high resistance) epitaxial layer (hereinafter sometimes simply referred to as an epi layer) is formed on a high concentration (low resistance) silicon substrate. P ⁺ epitaxial wafer (hereinafter referred to as P on ^{P +} epitaxial wafer) is used, also P on P in terms of cost to form the low concentration epitaxial layer at a low concentration on the substrate ^- epitaxial wafer (hereinafter, P on P ^- to as epitaxial wafer) is used. That is, the P on P ⁺ epi wafer has a problem in terms of cost, and the P on P ⁻ epi wafer has a problem in terms of gettering capability. That is, since a P on P ⁺ epiwafer uses a substrate doped with impurities at a high concentration, there is a problem such as auto-doping when a silicon epilayer is grown on the substrate. In order to avoid this, processing such as forming an oxide film on the back surface of the wafer is required, and since the P ⁺ crystal is stiff, the polishing time is longer than that of the P ⁻ substrate and the substrate cost is increased. On the other hand, the P on P ^- epi wafer does not cause the above-mentioned problem, but since a low concentration substrate is used, the gettering capability is low, and oxygen precipitation nuclei in the crystal disappear during high temperature epitaxial growth. As a result, the gettering ability further declined. In order to avoid this decrease in gettering ability due to the disappearance of oxygen precipitate nuclei, heat treatment to form oxygen precipitate nuclei is performed before epitaxial growth, or the crystal is pulled up by tuning the oxygen concentration during single crystal production. This complicates the process and results in an expensive epitaxial wafer.

  By the way, as a method different from the above-described gettering method, there has been proposed a Si on SiGe on Si epi-wafer in which a SiGe layer and a Si layer are sequentially epitaxially grown on a silicon substrate (Non-patent Document 1). This utilizes the fact that a SiGe layer having a large lattice constant causes misfit dislocations at the interface with the upper and lower silicon layers, and this acts as a gettering site.

  Further, Patent Document 1 discloses an epitaxial wafer having the same configuration (Si on SiGe on Si) as described above. However, in the epitaxial wafer described in Patent Document 1, misfit dislocations are prevented from occurring in the SiGe layer. By expanding the lattice spacing of the layers in the direction perpendicular to the Si substrate, compressive strain is formed in the SiGe layer to improve the gettering capability.

  Patent Document 2 discloses a method of using not only Ge but also any one of C, Sn, and Pb or a combination thereof as a dopant for forming a gettering layer.

  However, even though any of the above epi-wafers is a wafer that focuses on the enhancement of gettering capability during the device process, it cannot always be said that it has sufficient gettering capability, and the manufacturing process is complicated. For this reason, the manufacturing cost is high.

Japanese Patent Laid-Open No. 2004-281159 JP 2006-216934 A Semiconductor silicon crystal engineering p. 358 Published by Maruzen Fumio Shimura

  The present invention has been made in view of the above-described circumstances, and provides a high-quality silicon epitaxial wafer having a high gettering capability and leading to a reduction in the total cost of manufacturing a semiconductor device, and a method for manufacturing the same. Objective.

  In order to achieve the above object, in the present invention, a silicon epitaxial wafer comprising at least a strained SiGe layer on a silicon substrate, a Si protective layer on the strained SiGe layer, and an epitaxial Si layer on the Si protective layer. A high-concentration Si layer is provided between at least one of the silicon substrate and the strained SiGe layer and between the Si protective layer and the epitaxial Si layer. A silicon epitaxial wafer is provided (claim 1).

As described above, the Si protective layer is provided on the strained SiGe layer, and the high concentration Si layer is provided between the silicon substrate and the strained SiGe layer and between at least one of the Si protective layer and the epitaxial Si layer. The silicon epitaxial wafer having a surface has good surface roughness (haze) and high gettering capability as compared with a silicon epitaxial wafer having a conventional Si on SiGe on Si structure. This is because the surface roughness of the strained SiGe layer is covered with a Si protective layer, so that the effect of preventing surface roughness deterioration is obtained. In addition, the silicon epitaxial wafer according to the present invention has a high-concentration Si layer. Gettering ability is higher than that of single layer.
Note that the high-concentration Si layer refers to a Si layer having an impurity concentration of at least 5 × 10 ¹⁷ atoms / cm ³ .

In this case, it is preferable that the high-concentration Si layer is a P ⁺ layer.

Thus, if the high-concentration Si layer is a P ⁺ layer, it functions as an effective gettering site in the silicon epitaxial wafer in addition to the strained SiGe layer, and the gettering capability can be improved. Further, as will be described in detail below, since the film thickness of the epi layer can be easily managed by an optical method by using the P ⁺ layer, the manufacturing cost of the semiconductor device using the silicon epitaxial wafer according to the present invention is reduced. An effect etc. are acquired.

  Moreover, it is preferable that the Ge concentration of the strained SiGe layer is 10% or less and the thickness of the strained SiGe layer is 0.3 μm or less.

  Thus, if the Ge concentration of the strained SiGe layer is 10% or less and the thickness thereof is 0.3 μm or less, it is possible to suppress the occurrence of misfit dislocations in the strained SiGe layer. At the same time, the deterioration of surface roughness (haze) can be minimized.

Moreover, it is preferable that the thickness of the P ⁺ layer is larger than 0.25 μm.

Thus, if the thickness of the P ⁺ layer is made larger than 0.25 μm, the epitaxial thickness can be measured by a normal optical technique, and the thickness control of the epitaxial layer of the silicon epitaxial wafer according to the present invention can be performed. It becomes easy.

  The present invention also provides a method for producing a silicon epitaxial wafer, the step of forming a strained SiGe layer on at least a silicon substrate, the step of forming a Si protective layer on the strained SiGe layer, and an epitaxial layer on the Si protective layer. Forming a Si layer, and forming a high-concentration Si layer between at least one of the silicon substrate and the strained SiGe layer and between the Si protective layer and the epitaxial Si layer. A method for producing a silicon epitaxial wafer, characterized by comprising the steps (Claim 5).

  As described above, since the high-concentration Si layer is formed by epitaxial growth, contamination by a dopant such as auto-doping in a later step can be significantly suppressed as compared with the case where a conventional high-concentration Si substrate is used. Further, gettering ability can be imparted to a position (depth) closer to the epi layer.

In this case, in the step of forming the strained SiGe layer, the growth temperature is set to 750 ° C. or less, and any one of Si source gas of SiH ₄ , Si ₂ H ₆ , DCS, and TCS, and any of GeH ₄ and GeCl ₄ are used. This can be performed in combination with a Ge source gas.

In this way, the growth temperature of the strained SiGe layer is set to 750 ° C. or lower in order to prevent dislocation from occurring in the SiGe layer. Further, if a strained SiGe layer is formed by a combination of Si source gas of SiH ₄ , Si ₂ H ₆ , DCS, and TCS and Ge source gas of GeH ₄ or GeCl ₄ , any one of the above Since source gas is also generally used, there is an advantage that it can be easily handled and managed.

  The conditions for forming the Si protective layer are preferably the same as the conditions for forming the strained SiGe layer except that the supply of the Ge source gas is stopped.

  By doing so, the Si protective layer can be laminated immediately after the formation of the strained SiGe layer, and deterioration of the haze level on the surface of the strained SiGe layer can be minimized.

The high-concentration Si layer is preferably a P ⁺ layer.

Thus, if the high-concentration Si layer is a P ⁺ layer, high gettering capability can be ensured and the epitaxial thickness in the wafer diameter direction can be measured by a normal optical method. Management or quality assurance becomes easy.

  Furthermore, in the present invention, there is provided a semiconductor device manufacturing method using the silicon epitaxial wafer of the present invention, wherein at least an element is formed on the silicon epitaxial wafer, and a thinning process of the wafer on which the element is formed. And controlling the wafer thickness by an optical technique using the high-concentration Si layer during the thinning step and / or performing an etch stop using the strained SiGe layer of the silicon epitaxial wafer. A method for manufacturing a semiconductor device is provided.

As described above, the silicon epitaxial wafer according to the present invention has a high gettering capability and can easily measure the thickness of the wafer by an optical method using a high concentration Si layer. The thinning process in the back wrap performed later can be easily performed. Further, the strained SiGe layer can be used as an etch stop layer in the thinning process.
As described above, when the silicon epitaxial wafer according to the present invention is used for a semiconductor device, not only has a high gettering capability, but also can be effectively used in various processes of device and chip manufacturing, and an improvement in product yield and cost. Can contribute to reduction.

  In this case, it is preferable that the optical method is an FT-IR method.

  As described above, if the FT-IR (Fourier Transform Infrared Spectroscopy) method is used, the epitaxial thickness can be measured easily and accurately without contact, and the quality control of the product epi-wafer becomes possible.

  Furthermore, in the present invention, there is provided an SOI wafer manufacturing method using the silicon epitaxial wafer of the present invention, wherein the silicon epitaxial wafer is used as a bond wafer or a base wafer to manufacture an SOI wafer by a wafer bonding method. (Claim 11).

  Since the silicon epitaxial wafer according to the present invention has the advantages as described above, if it is used as a bond wafer (a wafer for forming an SOI layer) or a base wafer (a wafer for supporting an SOI layer), a high quality is obtained. An SOI wafer can be manufactured at a relatively low cost.

  Since the silicon epitaxial wafer according to the present invention has one or two high-concentration Si layers, the gettering capability is higher than that of a normal epitaxial wafer having only a strained SiGe layer as a gettering site. In addition, using this high-concentration Si layer, the film thickness distribution of the epitaxial layer in the diameter direction of the wafer can be easily measured and monitored by an optical technique such as FT-IR. It can be carried out easily and accurately, the film thickness management in the subsequent device process can be simplified, and it can also be used in the thinning process after device formation, contributing to improvement in product yield and cost reduction.

In addition, according to the method for manufacturing a silicon epitaxial wafer according to the present invention, it is possible to significantly reduce the contamination of impurities such as auto-doping in the epi growth as compared with the method for manufacturing P on P ⁺ epi wafer. Moreover, by forming the Si protective layer immediately after forming the strained SiGe layer, it is possible to minimize the deterioration of the surface roughness (haze) of the strained SiGe layer, and finally the silicon epitaxial wafer having excellent flatness can be obtained. Obtainable.

In addition, if a semiconductor device is manufactured using the silicon epitaxial wafer according to the present invention, the thickness distribution of the epitaxial layer in the diameter direction of the wafer can be easily measured in a non-contact manner by an optical method using a high-concentration Si layer. In addition, wafer thickness management and wafer quality control can be easily performed in a thinning process or the like performed from the back side after the device region is formed. Further, since the strained SiGe layer can be used as an etch stop layer, it is possible to prevent the surface from being roughened by an etching process in the device process.
As described above, when the silicon epitaxial wafer is used, not only the gettering capability is high, but it can be effectively used in various processes of device and chip fabrication.

  In addition, if the silicon epitaxial wafer according to the present invention is used as a bond wafer or a base wafer of an SOI wafer and the SOI wafer is manufactured by the wafer bonding method, the above-described characteristics can be obtained, so that a high-quality SOI wafer can be manufactured. it can.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, but the present invention is not limited to these descriptions.
FIG. 1 is a schematic view of a silicon epitaxial wafer according to the present invention. (A)-(c) has each shown three types of aspects of this invention.
As a typical example of the three types of embodiments of the present invention, a method for manufacturing a silicon epitaxial wafer illustrated in FIG. 1A will be described below. In FIGS. 1B and 1C, the method of FIG. Essentially the same as the manufacturing method.

In the present embodiment, a high resistance (low dopant concentration) substrate (hereinafter simply referred to as a P ^- substrate) 1 is used as a Si single crystal substrate prepared to avoid problems such as cost increase and autodoping.
The manufacturing method and the plane orientation of the P ⁻ substrate 1 may be appropriately selected according to the purpose, and are not particularly limited. For example, it is generally produced by a CZ (Czochralski) method or an FZ (Floating Zone) method.

Next, a strained SiGe layer 2 is epitaxially grown on the P ⁻ substrate 1, and as a pretreatment, a natural oxide film (not shown) on the surface of the P ⁻ substrate 1 is removed under an H ₂ atmosphere of about 1100 ° C., and thereafter The strained SiGe layer 2 is epitaxially grown at a Ge concentration at which the temperature is lowered to 750 ° C. or lower and no misfit dislocation occurs, preferably 10% or lower. At this time, it is preferable to use any one of SiH ₄ , Si ₂ H ₆ , DCS (dichlorosilane), and TCS (trichlorosilane) as the Si source gas, and GeH ₄ and GeCl ₄ as the Ge source gas. It is preferable to use any one of them.

Next, the Si protective film 3 is laminated on the strained SiGe layer 2. The stacked layers of the Si protective film 3 are desirably grown continuously under the same conditions after the epitaxial growth of the strained SiGe layer 2 is completed, with only the Ge source gas being cut off. This is to prevent the Si roughness layer 3 from deteriorating the surface roughness of the strained SiGe layer 2 during the temperature rise for the epitaxial growth of the P ⁺ layer 4, and immediately after the strained SiGe layer 2 is formed. This is because it is important.

After forming the Si protective layer 3, the temperature is raised to a predetermined temperature, and the epitaxial growth of the P ⁺ layer 4, which is a Si layer doped with acceptor impurities at a high concentration, is performed by adjusting to a desired resistivity. At this time, B is generally used as an acceptor impurity, but other dopants such as Ga can also be used.

Finally, a high resistance (low concentration) epitaxial Si layer 5 is formed on the P ⁺ layer 4 by adjusting to a desired resistivity at a predetermined temperature. In this way, a P on P ⁺ structure having a low concentration (high resistance) Si layer on a high concentration (low resistance) Si layer can be obtained.

As described above, the silicon epitaxial wafer according to the present invention includes not only a strained SiGe layer but also a high-concentration Si layer. Therefore, the silicon epitaxial wafer has a gettering site at the interface between the strained SiGe layer and the Si layer directly in contact therewith. At the same time, when B is used for the high-concentration Si layer, for example, it has a gettering capability of Fe or the like, so that a gettering capability higher than that of a single strained SiGe layer can be obtained. In addition, epi-growth is performed on the strained SiGe layer under conditions that do not cause misfit dislocations as much as possible, and a Si protective layer is immediately laminated, so that deterioration of the surface roughness can be minimized. Furthermore, in the present invention, the P on P ⁺ structure is realized by the epitaxial layer, so that the device region characteristic deterioration due to impurity auto-doping or the like can be suppressed as compared with the conventional case.

  The above silicon epitaxial wafer not only has a high gettering capability, but also uses a high-concentration Si layer in the wafer, and a non-contact and accurate epitaxial Si layer by a simple optical method (for example, FT-IR method). 5 can be measured, and quality control can be easily performed. That is, in the quality control of the epitaxial layer of the epitaxial wafer and the subsequent device formation process, the thickness of the wafer substrate is controlled during dry etching or CMP (Chemical Mechanical Polish) process, etc. It can also be used for thickness measurement when thinning by lapping. Further, the strained SiGe layer inherent in the wafer can be used as a stop layer for Si etching in the thinning process.

  As described above, the silicon epitaxial wafer according to the present invention not only has high gettering ability, but can be effectively used not only in the production of the epitaxial wafer but also in various processes from the subsequent element formation to chip fabrication. As a result, it is possible to contribute to improvement of product yield and cost reduction, and it is possible to manufacture a high-quality semiconductor device.

  Further, if an SOI wafer is produced by a wafer bonding method using the silicon epitaxial wafer as a bond wafer or a base wafer, a high-quality SOI wafer can be produced for the above reasons. For example, if the epitaxial wafer is used as a bond wafer, a high quality epitaxial layer can be used as an SOI layer.

The structure of the silicon epitaxial wafer having the same effect as that of the above-described silicon epitaxial wafer includes a P ⁺ layer 4, a strained SiGe layer 2, a Si protective layer 3, and an epi-Si layer sequentially on the silicon (P ⁻ ) substrate 1. 5 may be stacked (FIG. 1B), or a P ⁺ layer 4, a strained SiGe layer 2, a Si protective layer 3, a P ⁺ layer 4, and an epi Si layer 5 in this order on the silicon substrate 1. The structure (FIG.1 (c)) which laminates | stacks may be sufficient. In this way, the position and number of P ⁺ layers can be changed according to the purpose. For example, the type of FIG. 1A is good for enhancing the gettering of the epi-Si layer, and the type of FIG. 1B is good when there is a concern about contamination from the substrate. If it is desired to further enhance the gettering ability, the type shown in FIG.

In order to manufacture such an epitaxial wafer of the type shown in FIGS. 1B and 1C, a silicon substrate 1 is prepared, and the P ⁺ layer 4 is epitaxially grown before the step of forming the strained SiGe layer 2. What is necessary is just to perform a process.

Hereinafter, the present invention will be described in more detail with reference to experimental examples.
(Test 1)
<Relationship between Ge concentration and haze of strained SiGe layer and effectiveness of Si protective layer>

A P ⁻ (high resistance silicon single crystal) substrate 1 having a plane orientation {100} manufactured by the CZ method was prepared (FIG. 2). Then, the P ^- using the substrate 1 single-wafer CVD apparatus, _{H 2} atmosphere at 80 torr (about 11 kPa) vacuum conditions, was carried out with _{H 2} bake 1100 ° C.. Thereafter, the temperature is lowered to 690 ° C., and strains of Ge concentration of 7.5%, 9.1%, and 12.3% are applied on the P ^- substrate 1 under the conditions of SiH ₄ : 150 sccm, GeH ₄ : 10, _{40, and} 80 sccm, respectively. A SiGe layer 2 was formed (FIG. 2). Next, only the GeH ₄ gas was stopped to form an 18 nm Si protective layer 3 (FIG. 2). When the haze level was measured for each Ge concentration sample at this time, all were good at about 0.25 ppm (the upper part of FIG. 3). After the formation of the Si protective film 3, the SiH ₄ gas was stopped, the temperature was raised to 1080 ° C. in an H ₂ atmosphere, and an epitaxial Si layer 5 of about 1 μm was grown at DCS: 450 sccm (FIG. 2). As shown in the lower part of FIG. 3, the haze level of the wafer at that time deteriorates as the Ge concentration increases to 9.1% and 12.3%, and when the Ge concentration is 7.5%, It was found that the haze level was similar.

It has been confirmed that even in the case of a sample having a Ge concentration of 7.5%, if the temperature is raised to 1080 ° C. without performing the Si protective film 3 and epi-growth is performed, the haze level is deteriorated so that it cannot be measured. As described above, it was revealed that the Si protective layer 3 on the surface of the strained SiGe layer 2 is extremely important in order not to deteriorate the surface roughness (haze) of the strained SiGe layer 2.
(Test 2)
<Relationship between strained SiGe layer thickness and haze>

A P ⁻ (high resistance silicon single crystal) substrate 1 having a plane orientation {100} manufactured by the CZ method was prepared (FIG. 2). Then, P ^- substrate 1 by using a single-wafer CVD apparatus was conducted an _{H 2} atmosphere, 80 torr (about 11 kPa) under a reduced pressure, and _{H 2} bake at 1100 ° C.. Thereafter, the temperature is decreased to 690 ° C., and a strained SiGe layer having a thickness of 38 nm, 76 nm, and 152 nm is formed on the P ⁻ substrate 1 under conditions of SiH ₄ : 150 sccm and GeH ₄ : 10 sccm, respectively, with a Ge concentration of 7.5%. 2 was formed (FIG. 2). Subsequently, only the GeH ₄ gas was stopped, and an 18 nm Si protective layer 3 was formed (FIG. 2). At this time, the haze level of the strained SiGe layer 2 of each thickness was good at about 0.25 ppm (the upper part of FIG. 4). Next, after the Si protective layer 3 was formed, the SiH ₄ gas was stopped, the temperature was raised to 1080 ° C. in an H ₂ atmosphere, and an epi-Si layer 5 of about 1 μm was grown at DCS: 450 sccm. As a result of measuring the haze level of the wafer at that time, under the condition that the Ge concentration is 7.5%, the deterioration of the haze level of the Si layer 5 after the epitaxial growth is not seen until the thickness of the strained SiGe layer 2 is 152 nm, It was found to be the same level as that of a normal epi wafer (lower part of FIG. 4).

In the sample having a Ge concentration of 9.1% in the lower part of FIG. 3, the haze tends to partially deteriorate even when the thickness of the strained SiGe layer 2 is 128 nm, and a good haze level is obtained even after the growth of the epi-Si layer 5. In order to guarantee, it is assumed that the Ge concentration needs to be suppressed to 10% or less even if it is high.
(Test 3)
<Epitaxial thickness distribution measurement in wafer diameter direction by FT-IR using P ⁺ layer>

A P ⁻ (high resistance silicon single crystal) substrate 1 having a plane orientation {100} manufactured by the CZ method was prepared (FIG. 5A). Then, P ^- substrate 1 by using a single-wafer CVD apparatus, _{H 2} atmosphere at 80torr vacuum conditions, was carried out with _{H 2} bake 1100 ° C.. Thereafter, the temperature is lowered to 1000 ° C., and the P ⁺ layer 4 (resistivity 0.01 Ωcm) is adjusted to 0.25 μm on the P ⁻ substrate 1 by adjusting the time under the conditions of DCS: 200 sccm, 100 ppm B ₂ H ₆ : 170 sccm. , 0.5 μm, and 1.0 μm (FIG. 5A). Next, an epi-Si layer 5 (resistivity: 10 Ωcm) having a thickness of 5 μm was grown on the P ⁺ layer 4 at 1080 ° C. and DCS: 450 sccm. The film thickness distribution of the epi-Si layer 5 in the wafer diameter direction of each sample thus obtained was measured by an optical method (FT-IR method) (FIG. 5B). When a sample obtained by epitaxially growing a Si layer on a P ⁺ silicon substrate under the same condition is used as a reference, a sample obtained by growing a P ⁺ layer 4 on a P ⁻ substrate 1 by 1 μm exhibits almost the same value, and a 0.5 μm sample. Shows a slightly lower value, and the sample of 0.25 μm was not measurable.

From the results thus obtained, if the P ⁺ layer 4 is about 1 μm, it is possible to accurately measure the epi thickness by a normal optical method, and monitoring is sufficiently possible even when the P ⁺ layer 4 is 0.5 μm. I understood it. In addition, although the sample of 0.25 μm could not be measured under the current measurement conditions, there is still a possibility that measurement can be performed by changing the measurement conditions.
(Test 4)
<B depth profile and measurement of wafer resistivity by CV method>

In this experimental example, a sample having a P ⁺ layer 4 of 1 μm used in Test 3 was used. The profile of the B concentration in the depth direction (FIG. 6) and the resistivity of the 5 μm P ^- epi Si layer 5 by the SIMS (Secondary Ion Mass Spectrometer) at the wafer center and edge of this sample were measured by the CV (Capacitance Voltage) method. The central part, R / 2 part, and edge part were measured (FIG. 7).

The wafer thickness (center part 4.38 μm, edge part 4.69 μm) measured by the FT-IR method corresponds to a B concentration of 5 × 10 ¹⁸ / cm ³ as shown by the results of SIMS measurement. In the case where the concentration is lower than this concentration, it cannot be measured by the FT-IR method. That is, when B is an acceptor impurity in order to form the P ⁺ layer, a concentration of at least 5 × 10 ¹⁸ / cm ³ or more is required (see the arrows shown in FIG. 6). Further, in this sample, it was found that CV measurement can be performed well as shown in FIG. 7, and the P ⁺ epiwafer on the P ⁻ substrate can also be used as a monitor wafer for epitaxial thickness and resistivity measurement in epitaxial manufacturing.

As described above, from the results obtained in Test 1 to Test 4, the silicon epitaxial wafer according to the present invention preferably has a Ge concentration of the strained SiGe layer of 10% or less, and immediately after the formation of the strained SiGe layer, the Si protection is performed. It was found that forming a layer is important in terms of suppressing deterioration of surface roughness. Furthermore, by making good use of the high-concentration Si layer, the epitaxial thickness in the wafer diameter direction can be easily measured by an optical method. At this time, if an FT-IR method, for example, is used as an optical method, the epi thickness can be measured easily and accurately. Incidentally, in the case of measuring the film thickness FT-IR method preferably is better to thicker than 0.25μm The ^{P +} layer, if epitaxial layer thickness of about 1μm in ^{the P +} layer, epitaxial layer thickness measurement and the CV measurement Since the same result as in the case of the P ⁺ substrate was obtained, it was shown that the substitution of the P ⁺ substrate is sufficiently possible.

Examples of the present invention will be specifically described below, but the present invention is not limited to the following examples.
(Examples 1, 2, and 3)
A silicon epitaxial wafer having a structure as shown in FIG. 1A was manufactured as follows.
First, a P ⁻ (high resistance silicon single crystal) substrate 1 having a plane orientation {100} manufactured by the CZ method was prepared. Then, the P ^- using the substrate 1 single-wafer CVD apparatus, _{H 2} atmosphere at 80 torr (about 11 kPa) vacuum conditions, was carried out with _{H 2} bake 1100 ° C.. Thereafter, the temperature was lowered to 690 ° C., and a strained SiGe layer 2 having a Ge concentration of 7.5% was formed on the P ⁻ substrate 1 under the conditions of SiH ₄ : 150 sccm and GeH ₄ : 10 sccm. Next, only the GeH ₄ gas was stopped to form an 18 nm Si protective layer 3. Thereafter, the temperature is raised to 1000 ° C., and the P ⁺ layer 4 (resistivity 0.01 Ωcm) is adjusted to 1.0 μm on the Si protective layer 3 by adjusting the time under the conditions of DCS: 200 sccm, 100 ppm B ₂ H ₆ : 170 sccm. Formed. Further, an epi-Si layer 5 (resistivity: 10 Ωcm) having a thickness of 5 μm was grown on the P ⁺ layer 4 at 1080 ° C. and DCS: 450 sccm to obtain a final silicon epitaxial wafer (Example 1).

Further, a silicon epitaxial wafer having a structure as shown in FIG. 1B was manufactured as follows.
First, a P ⁻ (high resistance silicon single crystal) substrate 1 having a plane orientation {100} manufactured by the CZ method was prepared. Then, the P ^- using the substrate 1 single-wafer CVD apparatus, _{H 2} atmosphere at 80 torr (about 11 kPa) vacuum conditions, was carried out with _{H 2} bake 1100 ° C.. Next, the temperature is lowered to 1000 ° C., and the P ⁺ layer 4 (resistivity 0.01 Ωcm) is adjusted to 1.0 μm on the P ⁻ substrate 1 by adjusting the time under the conditions of DCS: 200 sccm, 100 ppm B ₂ H ₆ : 170 sccm. Formed. Thereafter, the temperature was lowered to 690 ° C., and a strained SiGe layer 2 having a Ge concentration of 7.5% was formed on the P ⁺ layer 4 under conditions of SiH ₄ : 150 sccm and GeH ₄ : 10 sccm. Next, only the GeH ₄ gas was stopped to form an 18 nm Si protective layer 3. Further, an epi-Si layer 5 (resistivity: 10 Ωcm) of 5 μm was grown on the Si protective layer 3 at 1080 ° C. and DCS: 450 sccm to obtain a final silicon epitaxial wafer (Example 2).

Further, a silicon epitaxial wafer having a structure as shown in FIG. 1C was manufactured as follows.
First, the Si protective layer 3 was formed by the same process as in Example 2. Thereafter, the temperature is raised to 1000 ° C., and the P ⁺ layer 4 (resistivity 0.01 Ωcm) is again formed on the Si protective layer 3 by adjusting the time under the conditions of DCS: 200 sccm, 100 ppm B ₂ H ₆ : 170 sccm. 0 μm was formed. Further, an epi-Si layer 5 (resistivity: 10 Ωcm) having a thickness of 5 μm was grown on this P ⁺ layer 4 at 1080 ° C. and DCS: 450 sccm to obtain a final silicon epitaxial wafer (Example 3).

The hazes of the epitaxial Si layer 5 of the silicon epitaxial wafer manufactured in Examples 1, 2, and 3 are shown in FIGS. 8A, 8B, and 8C, respectively. The haze level was 0.26 ppm and was good.
Moreover, the film thickness distribution of the epitaxial Si layer 5 in the wafer diameter direction of the silicon epitaxial wafer manufactured in Examples 1, 2, and 3 was measured by an optical method (FT-IR method). The results are shown in (a), (b), and (c) of FIG. Due to the presence of the P ⁺ layer, the film thickness distribution of the epi-Si layer 5 could be measured.

Further, the gettering ability of the epitaxial wafer of Example 1 according to the present invention was evaluated as follows.
First, a reference epitaxial wafer as shown in FIGS. 10A and 10B, that is, an epitaxial wafer in which an epitaxial Si layer is grown on a P ⁺ substrate as reference 1 and a wafer of Example 1 as reference 2 An epitaxial wafer excluding the ⁺ layer was manufactured. The growth conditions of the layers of the epitaxial wafers of Reference 1 and 2 were the same as in the examples.

Ni and Fe were applied at a concentration of about 5 × 10 ¹² atoms / cm ^{2 on} the surface of each of the epitaxial wafer of Example 1 and the epitaxial wafers of References 1 and 2, and were diffused inside by heat treatment for 1 hour. Next, the Si layer near the surface was etched, and the Ni and Fe concentrations in the solution were measured by ICP-MS. Table 1 shows the metal concentration on each wafer surface.

An epitaxial wafer obtained by growing an epitaxial Si layer on the P ⁺ substrate of Reference 1 has a gettering ability for Fe, but no gettering effect was observed for Ni. The wafer which does not form the P ⁺ layer of Reference 2 has a gettering ability for Ni due to the strained SiGe layer, but has a low ability for Fe because there is no P ⁺ layer. On the other hand, it was found that the wafer of Example 1 has high gettering ability for both Ni and Fe.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and any technique that has substantially the same configuration as the technical idea described in the claims of the present invention and has the same operational effects can be used. To be included in the scope.

(A)-(c) is the schematic which shows the structure of the silicon epitaxial wafer in all this invention. It is the schematic which shows the structure of the silicon epitaxial wafer in Test 1 and 2. (Example 1) which was the figure which showed the relationship of Ge density | concentration and thickness of a strained SiGe layer, and haze. It is a figure which shows the relationship between the thickness of a strained SiGe layer, and haze when the Ge density | concentration of a strained SiGe layer is made constant (test 2). (A) It is the schematic which shows the structure of the silicon epitaxial wafer in the test 3. FIG. (B) It is the graph which showed the result of the epitaxial thickness distribution measurement of the wafer diameter direction by FT-IR method (test 3). It is a figure which shows the relationship between the epi-thickness distribution map measured by FT-IR method, and the result of having measured the profile of the depth direction of B (test 4). It is a graph which shows the result of the CV resistivity measurement of the P ^- substrate of the silicon epitaxial wafer in Test 4. It is the figure which showed the haze of the epitaxial Si layer surface. (A) Example 1, (b) Example 2, (c) Example 3. It is the graph which showed the result of the epi thickness distribution measurement of the wafer diameter direction by FT-IR method. It is the schematic which showed the structure of the reference epitaxial wafer used in the case of evaluation of gettering capability, (a) is the epitaxial wafer which grew the epitaxial Si layer on the P ⁺ board | substrate, (b) is implementation 3 is an epitaxial wafer obtained by removing the P ⁺ layer from the wafer of Example 1.

Explanation of symbols

1 ... P ^- (silicon) substrate, 2 ... strained SiGe layer, 3 ... Si protective layer (film), 4 ... ^{P +} layer, 5 ... epitaxial Si layer (P ^- epitaxial layer).

Claims (11)

  A silicon epitaxial wafer comprising at least a strained SiGe layer on a silicon substrate, a Si protective layer on the strained SiGe layer, and an epitaxial Si layer on the Si protective layer, the silicon substrate and the strained SiGe A silicon epitaxial wafer comprising a high-concentration Si layer between layers, and at least one between the Si protective layer and the epitaxial Si layer. The silicon epitaxial wafer according to claim 1, wherein the high-concentration Si layer is a P ⁺ layer.   3. The silicon epitaxial wafer according to claim 1, wherein a Ge concentration of the strained SiGe layer is 10% or less, and a thickness of the strained SiGe layer is 0.3 μm or less. 4. The silicon epitaxial wafer according to claim 2, wherein a thickness of the P ⁺ layer is larger than 0.25 μm. 5.   In the method for manufacturing a silicon epitaxial wafer, at least a step of forming a strained SiGe layer on a silicon substrate, a step of forming a Si protective layer on the strained SiGe layer, and a step of forming an epitaxial Si layer on the Si protective layer And forming a high-concentration Si layer between at least one of the silicon substrate and the strained SiGe layer and between the Si protective layer and the epitaxial Si layer. A method for producing a silicon epitaxial wafer. In the step of forming the strained SiGe layer, the growth temperature is set to 750 ° C. or lower, the Si source gas of SiH ₄ , Si ₂ H ₆ , DCS, and TCS, and the Ge source of GeH ₄ and GeCl ₄ The method for producing a silicon epitaxial wafer according to claim 5, wherein the method is performed in combination with a gas.   The conditions for forming the Si protective layer are the same as the conditions for forming the strained SiGe layer except that the supply of the Ge source gas is stopped. A method for producing a silicon epitaxial wafer as described. The method for producing a silicon epitaxial wafer according to claim 5, wherein the high-concentration Si layer is a P ⁺ layer.   A method of manufacturing a semiconductor device using the silicon epitaxial wafer according to any one of claims 1 to 4, wherein the element is formed on at least the silicon epitaxial wafer, and the element is formed. The wafer thinning step, and using the high-concentration Si layer during the thinning step to manage the wafer thickness by an optical technique, and / or using the strained SiGe layer of the silicon epitaxial wafer Etching stop is performed, The manufacturing method of the semiconductor device characterized by the above-mentioned.   The method of manufacturing a semiconductor device according to claim 9, wherein the optical method is an FT-IR method.   An SOI wafer manufacturing method using the silicon epitaxial wafer according to any one of claims 1 to 4, wherein the silicon epitaxial wafer is used as a bond wafer or a base wafer to perform SOI bonding by a wafer bonding method. A method of manufacturing a wafer.

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