200845142 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種能夠使用於MOS元件之高吸氣 蠢晶石夕晶圓及其製造方法、以及使用其之半導體元件的製 造方法及SOI晶圓的製造方法。 【先前技術】 M0S元件用磊晶矽晶圓，一年一年地往大口徑化進 展’目前以3 00毫米晶圓為主流。而且，對（1)元件形成區 域的完全性、（2)高吸氣能力、及（3)低成本化的要求越來 越強烈°從閉鎖（latch-up)耐性及吸氣能力的觀點，先前是 使用在P型高濃度（低電阻）矽基板上形成有p型低濃度（高 電阻）遙晶層（以下亦有簡稱為磊晶層之情況）之P+上覆P 蠢晶晶圓（以下，記載為p+上覆p磊晶晶圓（p 〇n P + epiwafer));又，從成本的觀點，是使用在p型低濃度矽基 板上形成有p型低濃度磊晶層之p-磊晶晶圓上覆p(以下， 5己載為P上覆P蟲晶晶圓（P on P.epiwafer))。亦即，p + 上覆P蠢晶晶圓有成本方面的課題，ρ·上覆p磊晶晶圓有 吸氣能力方面的課題。亦即，因為P+上覆P磊晶晶圓是使 用雨濃度換合不純物而成的基板，所以在該基板上成長磊 • 晶層時’會有自動摻雜等之問題。為了避免此問題，必須 在晶圓背面進行形成氧化膜等之處理，又，因為p+結晶較 硬，與P比較時須要較長的研磨時間，致使基板成本提高。 另方面雖然P上覆P遙晶晶圓不會產生如上述問題， 5 200845142 但是因為使用低濃度基板，所以吸氣能力差，又，在高溫 磊晶成長時，因為結晶中的氧析出核消滅掉，造成吸氣能 力更為降低〇為了避免因該氧析出核消滅而造成吸氣能力 降低’必須在磊晶成長前進行形成氧析出核之熱處理，或 是在製造單結晶時，必須調準氧濃度而拉升結晶致使製程 複雜化’結果成為高成本的蠢晶晶圓。 且說，有一種與上述吸氣手法不同之方法，有提案（半 導體矽結晶工程學第358頁、丸善股份公司發行、志村史 夫著）揭示一種矽上覆矽鍺覆矽磊晶晶圓（Si 〇n SiGe on Si epiwafer)，是在矽基板上依照順序使siGe層、Si層磊晶 成長來層積而成。其是藉由晶格常數大的SiGe層並使其在 與上下的矽層的界面產生不良位錯，且將該等不良位錯利 用作為吸氣區域使用。 又，在特開2004-281 591號公報揭示一種與上述相同 構成（矽上覆矽鍺覆矽；Si on SiGe on Si)的磊晶晶圓，但 是特開2004-28 1 591號公報之磊晶晶圓是未使SiGe層產生 不良位錯，而是藉由使SiGe層的晶格間隔往與矽基板垂直 方向擴展，使SiGe層產生壓縮應變來謀求提高吸氣能力。 又，在特開2004-281591號公報揭示一種方法，用以 形成吸氣層之摻雜物不只是Ge，亦組合C、Sn及Pb中任 一者或該等而使用。 但是，上述任一者的磊晶晶圓儘管是注目於強化元件 製程中的吸氣能力而成之晶圓，但是不一定能夠稱為具有 充分的吸氣能力，又，因為其製程麻煩等，具有製造成本 6 200845142 高的缺點。 【發明内容】 本發明是鑒於上述情形而開發出來，其目的是提供一 種高品質的磊晶矽晶圓及其製造方法，該磊晶矽晶圓具有 高吸氣能力，且可降低半導體元件製造的總成本。 為了達成前述目的，本發明提供一種磊晶碎晶圓，其 特徵為：是至少在矽基板上具備應變 SiGe層、在該應變 SiGe層上的Si保護層、及在該Si保護層上的磊晶Si層之 磊晶矽晶圓，其中在上述矽基板與上述應變SiGe層之間、 及在上述Si保護層與上述磊晶 Si層之間的至少一方之 間，具備高濃度Si層。 如此，在應變SiGe層上具有Si保護層，又，在上述 矽基板與上述應變SiGe層之間、及在上述Si保護層與上 述磊晶Si層之間的至少一方之間，具備高濃度Si層之磊 晶矽晶圓，與先前的矽上覆矽鍺覆矽（Si on SiGe on Si)結 構的磊晶矽晶圓比較時，表面粗糙度（霧度）良好且具有高 吸氣能力。這是因為藉由Si保護層覆蓋應變SiGe層的表 面，能夠得到防止表面粗糙度惡化的效果，又，因為本發 明之磊晶矽晶圓具有高濃度Si層，與先前的單層應變SiGe 層比較時，吸氣能力較高。 又，所謂的高濃度Si層，是指不純物濃度至少為5x 1017atoms/cm3 之 Si 層。 此時，前述高濃度Si層以P +層為佳。 7 200845142 如此，若高濃度Si層是p +層時’並且亦加上上述應 變SiGe層，在上述磊晶矽晶圓内能夠使用作為有效的吸氣 區域，能夠謀求提高吸氣能力。又，將在以下詳細說明，P + 層時因為藉由光學手法能夠使磊晶層的膜厚度管理變為容 易，本發明之使用磊晶矽晶圓來製造半導體元件能夠得到 削減的成本之效果。 又，上述應變SiGe層的Ge濃度以1〇°/❶以下、且上述 應變SiGe層的厚度以0.3微米以下為佳。 如此，使應變SiGe層的Ge濃度為10%以下、且其厚 度為0.3微求以下時，能夠抑制在應變SiGe層中產生不良 錯位。又，同時亦能夠抑制表面粗糙度（霧度）的惡化。 又’上述P +層的厚度以大於0.25微米為佳。 如此，使P +層的厚度大於0.25微米時，藉由通常的 光學手法，能夠測定磊晶厚度，能夠使本發明之磊晶層的 膜厚度管理變為容易。 又，本發明是提供一種磊晶矽晶圓的製造方法，是製 〇 造遙晶發晶圓的方法，其特徵是至少具有以下製程，包含： 在石夕基板上形成應變SiGe層之製程；在該應變SiGe層上 形成si保護層之製程；及在該Si保護層上形成磊晶si層 之製程；並且具有在上述矽基板與上述應變siGe層之間、 及在上述Si保護層與上述磊晶層之間的至少一方之 間’形成高濃度Si層之製程。 如此’因為高濃度Si層的形成是藉由磊晶成長來進 行’與先前使用高濃度基板比較，能夠大幅度地抑制在後 8 200845142 面的製程因自動摻雜 於雜所引起的污染。又，能夠在接近磊晶 層的位置（深度）賦； %予吸氣能力。 此時，形成上奸 建應變SiGe層之製程，能夠藉由使成長 溫度為750°C以下、 ^ ^ ’迷組合 SiH4、Si2H6、DCS、及 TCS 之 任一者的Si源氣斜 、以及GeΗ4及GeC14之任一者的 源氣體來進行。 如此，使應變s i 防止在該SiGe層產生^ 及TCS之任一者200845142 IX. Description of the Invention: [Technical Field] The present invention relates to a high-intake oligocrystalline wafer which can be used for a MOS device, a method for fabricating the same, a method for manufacturing a semiconductor device using the same, and an SOI Wafer manufacturing method. [Prior Art] M0S components use epitaxial germanium wafers, and they are expanding to large diameters year after year. Currently, 300 mm wafers are the mainstream. Moreover, the requirements for (1) completeness of the element formation region, (2) high gas absorption capacity, and (3) low cost are becoming stronger and stronger. From the viewpoints of latch-up resistance and gas absorption capacity, Previously, P+ overlying P-type wafers were formed using a p-type low concentration (high resistance) crystal layer (hereinafter also referred to as an epitaxial layer) on a P-type high concentration (low resistance) germanium substrate ( Hereinafter, it is described as a p+ overlying p epitaxial wafer (p 〇n P + epiwafer); and, from the viewpoint of cost, a p-type low concentration epitaxial layer is formed on a p-type low-concentration germanium substrate. - The epitaxial wafer is overlaid with p (hereinafter, 5 is loaded with P over P. epiwafer). That is, there is a cost issue in the p + overlying P wafer, and the ρ· overlying p epitaxial wafer has a problem in the gas absorption capability. That is, since the P+ overlying P epitaxial wafer is a substrate obtained by replacing the impurity with a rain concentration, there is a problem of automatic doping when the epitaxial layer is grown on the substrate. In order to avoid this problem, it is necessary to perform an oxide film formation or the like on the back surface of the wafer, and since the p+ crystal is hard, a longer polishing time is required when compared with P, resulting in an increase in substrate cost. On the other hand, although the P-clad P-transparent wafer does not cause the above problems, 5 200845142 However, because of the low-concentration substrate, the gettering ability is poor, and at the time of high-temperature epitaxial growth, the oxygen-extracting nuclei in the crystal are eliminated. If it is dropped, the gettering ability is further reduced. In order to avoid the decrease of the gettering ability due to the elimination of the oxygen-precipitating nuclei, it is necessary to perform the heat treatment for forming the oxygen-precipitating nuclei before the epitaxial growth, or to adjust the production of the single crystal. The oxygen concentration and the crystallization of the crystals complicate the process' result as a high-cost amorphous wafer. It is said that there is a different method from the above-mentioned gettering method, and there are proposals (Semiconductor, Crystallization Engineering, p. 358, Maruzen Co., Ltd., and Shimura Shifu) to disclose an overlying tantalum epitaxial wafer (Si 〇 n SiGe on Si epiwafer) is formed by laminating the SiGe layer and the Si layer in order on the germanium substrate. This is because the SiGe layer having a large lattice constant causes undesirable dislocations at the interface with the upper and lower ruthenium layers, and these mis-dislocations are used as the gettering regions. Japanese Laid-Open Patent Publication No. 2004-281 591 discloses an epitaxial wafer having the same configuration as that described above (Si on SiGe on Si), but it is disclosed in Japanese Patent Publication No. 2004-28 1 591 The crystal wafer does not cause undesirable dislocations in the SiGe layer, but expands the lattice spacing of the SiGe layer in the direction perpendicular to the germanium substrate, thereby causing compressive strain in the SiGe layer to improve the gettering ability. Further, Japanese Laid-Open Patent Publication No. 2004-281591 discloses a method in which a dopant for forming a gettering layer is used not only as Ge but also any one of C, Sn and Pb or the like. However, although the epitaxial wafer of any of the above is a wafer which is focused on the gettering ability in the process of the reinforced component, it may not necessarily be said to have sufficient inspiratory capability, and because of the troublesome process, etc. Has the disadvantage of high manufacturing cost 6 200845142. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a high quality epitaxial wafer having high gas absorption capability and reducing semiconductor element manufacturing. The total cost. In order to achieve the foregoing object, the present invention provides an epitaxial wafer having a strained SiGe layer on at least a germanium substrate, a Si protective layer on the strained SiGe layer, and a Lei on the Si protective layer. The epitaxial germanium wafer of the crystalline Si layer includes a high concentration Si layer between at least one of the germanium substrate and the strained SiGe layer and between the Si protective layer and the epitaxial Si layer. As described above, the Si-protective layer is provided on the strained SiGe layer, and a high-concentration Si is provided between the tantalum substrate and the strained SiGe layer and between at least one of the Si protective layer and the epitaxial Si layer. The layered epitaxial wafer has a good surface roughness (haze) and high gas absorption capacity when compared with the prior epitaxial germanium wafer with Sion SiGe on Si structure. This is because the surface of the strained SiGe layer is covered by the Si protective layer, and the effect of preventing the deterioration of the surface roughness can be obtained. Moreover, since the epitaxial germanium wafer of the present invention has a high concentration Si layer, and the previous single-layer strained SiGe layer When compared, the inspiratory capacity is higher. Further, the so-called high-concentration Si layer means a Si layer having an impurity concentration of at least 5 x 1017 atoms/cm3. At this time, the high-concentration Si layer is preferably a P + layer. 7 200845142 Thus, if the high-concentration Si layer is a p + layer' and the above-described strained SiGe layer is added, an effective gettering region can be used in the epitaxial germanium wafer, and the gettering ability can be improved. Further, as will be described in detail below, in the case of the P + layer, since the film thickness management of the epitaxial layer can be facilitated by an optical method, the effect of reducing the cost can be obtained by using the epitaxial germanium wafer for manufacturing a semiconductor device of the present invention. . Further, the strained SiGe layer has a Ge concentration of 1 〇 / ❶ or less, and the strained SiGe layer has a thickness of 0.3 μm or less. When the Ge concentration of the strained SiGe layer is 10% or less and the thickness is 0.3 or less, it is possible to suppress occurrence of defective misalignment in the strained SiGe layer. Further, it is also possible to suppress deterioration of surface roughness (haze). Further, the thickness of the above P + layer is preferably greater than 0.25 μm. As described above, when the thickness of the P + layer is more than 0.25 μm, the epitaxial thickness can be measured by a usual optical method, and the film thickness management of the epitaxial layer of the present invention can be facilitated. Moreover, the present invention provides a method for fabricating an epitaxial germanium wafer, which is a method for fabricating a germanium wafer, characterized in that it has at least the following processes, including: a process for forming a strained SiGe layer on a stone substrate; a process of forming a Si protective layer on the strained SiGe layer; and a process of forming an epitaxial Si layer on the Si protective layer; and having between the germanium substrate and the strained siGe layer, and the Si protective layer and the above A process of forming a high concentration Si layer between at least one of the epitaxial layers. Thus, since the formation of the high-concentration Si layer is carried out by epitaxial growth, it is possible to greatly suppress the contamination caused by the automatic doping of impurities in the process of the subsequent 8 200845142 surface as compared with the conventional use of the high-concentration substrate. Further, the position (depth) close to the epitaxial layer can be given a % pre-suction capability. At this time, a process for forming a strained SiGe layer can be formed by using a Si source gas slant which has a growth temperature of 750 ° C or less, a combination of SiH 4 , Si 2 H 6 , DCS , and TCS , and Ge Η 4 And the source gas of any of GeC14 is performed. Thus, the strain s i is prevented from generating either ^ and TCS in the SiGe layer.
Ge層的成長溫度為750°C以下是為了 錯位的緣故。組合SiH4、Si2H6、D(：S、 的Si源氣體、以及GeH4及GeCl4之你一 者的Ge源氣體來形上 ^ t仏成應變SiGe層時，因為上述任— 氣體都是通常使用而〜 m ^ 巧而容易處理等，且具有容易管理之僖赴 又，形成上述Q · 知 % Si保護層時的條件是除了停止供仏 源氣體以外，以與n 、μ ue n形成上述應變SiGe層時的條件相 佳。 τ日丨马 藉由如此進杆 . 订’在形成上述應變SiGe層後，能夠 層積Si保護層，故机 刻 Ο 犯夠將應變SiGe層表面的霧度水準 化，抑制至最小限度。 的恶 又’上述回遭度Si層以p +層為佳。 ^ 攻向濃度Si層為P +層時，因為能約擔保 阿吸亂能力，1¾時藉由通常的光學手法能夠測定晶圓直徑 方向的;εδ曰曰厚《，能夠使磊晶層的膜厚管理或品 變為容易。 筲保證 而 且，本發明是提供一種半導體元件的製造方法，其 特徵為：是使用上^ # 發明的蠢晶梦晶圓來製造半導體元 9 200845142 件的製造方法，至少具有在該蠢晶矽晶圓上形成元件之製 程、及將形成有該元件之上述晶圓薄化之製程；在該薄化 製程時，是使用上述高濃度Si層並藉由光學手法來管理晶 圓厚度、及/或使用上述蠢晶石夕晶圓的應變siGe層來進行 餘刻中止。 如上述，本發明之蠢晶石夕晶圓是具有高吸氣能力，又， 因為使用高滚度Si層’藉由光學手法能夠容易地測定晶圓 【、 厚度，在元件形成後進行背面磨光時，能夠簡便地進行薄 化製程。而且亦能夠在薄化製程中利用應變siGe層作為中 止層。 如此，將本發明之蠢晶石夕晶圓使用於半導體元件時， 不只是吸氣能力高，而且在製造元件、晶片之各式各樣的 製程中，亦能夠有效地利用，能夠有助於提高製品產率、 及降低成本。 此時，上述光學手法，以FT-IR法為佳。 如此’使用FT-IR (傅立葉變換紅外線光譜；F〇urier 〇 Transform Infrared Spectroscopy)法時，能夠以簡便且非接 觸的方式精確度良好地測定磊晶厚度，製品磊晶晶圓的品 質管理變為可能。 而且，本發明是提供一種製造s〇I晶圓之方法，是使 用前述本發明的磊晶矽晶圓之s〇i晶圓的製造方法，其中 將上述磊晶矽晶圓使用作為接合晶圓或基體晶圓並藉由晶 圓貼合方法來製造SOI晶圓。 因為本發明之磊晶矽晶圓具有上述的優點，利用其作 10 200845142 為接合晶圓（用以形成SOI層之晶圓）或是基體晶圓（用 撐SOI層之晶圓）時，能夠以較低的成本製造高品質的 晶圓。 因為本發明之磊晶矽晶圓具有1層或2層之高濃 層作為吸氣部位時，其吸氣能力比只有具備應變 層之通常的晶圓高。又，使用該高濃度Si層，因為 FT-IR等光學手法能夠簡便地測定、監控晶圓的直徑 的蠢晶層之膜厚度分布，所以能夠容易且正確地進行 層的膜厚度管理及品質保證，且在其後的元件製程的 度官理亦能夠簡便化，又，亦能夠利用於元件形成後 化製程’能夠有助於製品產率的提升及降低成本。 又’依照本發明的磊晶矽晶圓的製造方法時，與 覆P磊晶晶圓的製造方法比較，能夠大幅度地降低在 成長時自動摻雜等的不純物的混入。又，藉由在形成 SiGe層後’立刻形成si保護層，能夠使應變SiGe層 面粗植度（霧度）的惡化止於最低限度，最後能夠得到 性優良的磊晶矽晶圓。 又’使用本發明之磊晶矽晶圓來製造半導體元件 因為使用高濃度Si層，藉由光學手法能夠以非接觸的 容易地測定磊晶層的厚度分布，所以在元件區域形成 在從背面進行薄化製程等時，能夠簡便地進行晶圓厚 理及晶圓的品質管理。又，因為能夠將應變SiGe層作 止層，在元件製程時，亦能夠謀求防止因蝕刻所造成 面粗糙。 以支 SOI 度Si SiGe 藉由 方向 蠢晶 膜厚 的薄 P +上 羞晶 應變 的表 平坦 時， 方式 後， 度管 為中 的表 11 200845142 如此’使用上述的磊晶矽晶圓時，不只是吸氣能力高， 而且在元件、晶圓製造之各式各樣的製程中，亦能夠有效 利用® 又’將本發明之磊晶矽晶圓使用作為S 01晶圓的接合 晶圓或基體晶圓，並藉由晶圓貼合法來製造SOI晶圓時， 因為具有上述特性，能夠製造出高品質的S〇I晶圓。 【實施方式】 以下，一邊參照圖示一邊具體地說明本發明的實施形 癌’但是本發明未限定於這些記載。 第1圖是有關本發明的磊晶矽晶圓之概略圖。（a)〜 分別表示本發明的3種態樣。 作為本發明的3種態樣的代表例，以下說明第1圖（a) 所示之磊晶矽晶圓的製造方法，但是第1圖（b)、（c)在本質 上是與（a)的製造方法沒有改變。 在本實施形態，為了避免成本提高及自動摻雜等問題 所準備的S i單結晶基板，是使用p型高電阻（低摻雜濃度） 基板（以下簡稱P-基板）。 又’ P基板的製造方法及面方位等，只要配合目的而 適當地選擇即可，沒有特別限定。例如通常是依照CZ(切 克勞斯基，Czochralski)法或FZ(浮動區炼；Floating Zone) 法製造。 接著，使應變SiGe層2在厂基板1上進行磊晶成長， 其前處理是在11〇〇 t：左右的H2環境下，除去p-基板1表 12 200845142 面上的自然氧化臈（未圖示），隨後降溫至75〇t：以下並 以不會產生不良錯位（差排）之Ge漠度、較佳是以1〇%以下 的濃度’使應變SiGe層2蟲晶成長。此時，作為Si源氣 體，以使用81114、812116、0€8(二氣矽烷）及11(：3(三氣矽烷） 之任一種為佳，作為Ge源氣體，以使用^…及GeCU2 任一種為佳。 接著，使Si保護膜3層積在應變siGe層2上。si保 護膜3的層積，較佳是以在應變SiGe層2的磊晶成長結束 後，於只有遮蔽Ge源氣體且維持此狀態的條件，連續地 成長。這是因為Si保護層3，是為了在用以進行p +層4的 蠢晶成長的升溫中，使應變SiGe層2的表面粗糙度不會惡 化。因此’在應變SiGe層2形成後，立刻使其形成是重要 的。 形成S1保護層3後，升溫至規定溫度，並進行高濃度 地摻雜受體不純物（調整成為需要的電阻率）而成的si層亦 即P +層4的磊晶成長。此時，作為受體不純物，通常是使 用B(硼），但是亦可以用Ga(鎵）等其他的摻雜物。 最後，在P +層4上，於規定溫度以成為需要的電阻率 的方式進行調整，而形成高電阻（低濃度）的磊晶si層5。 如此進行，能夠得到在高濃度（低電阻）Si層上具有低濃度 (高電阻）Si層的結構也就是P +上覆p結構。 如此，有關本發明之磊晶矽晶圓，因為不只是應變 SiGe層而且亦具備高濃度si層，所以在應變SiGe層與在 其上下直接接觸的Si層之界面具有吸氣部位（gettering 13 200845142 site)，同時若在高濃度Si層例如使用b時 Fe等的吸氣能力(聚集能力），所以與單層的 時比較，能夠得到吸氣能力高之物…因 產生不良錯位的條件使該應變層磊晶W 刻層積Si保護層，所以能夠將其表面粗糙度 最小限度ϋ，本發明是藉由&晶層來實又 構’與先前的情況比較’能夠抑制因不純物 所引起之元件區域的特性劣化。 若是上述蠢晶梦晶圓時，不只是吸氣能 晶圓中的面濃度Si層’並藉由簡便的光學手 法）’便能约以非接觸的方式精確度良好地洋 5的膜厚度，能夠使該品質管理變為容易。 晶圓的磊晶層的管理、或在隨後之元件的形 夠利用於乾式#刻或CMP(化學機械研 Mechanical Polish)等製程時之膜厚度管理· 用於：在藉由磨光（lapping)元件製作後的晶 而使其薄化時之厚度測定。而且，内部存在 之應變S i G e層’在薄化製程時，亦能夠利^ 的中止層。 如此’本發明之蟲晶梦晶圓，不只是吸 不僅是可有效地利用於製造磊晶晶圓，也可 隨後的元件形成至晶片製作之各式各樣的製 夠有助於提高製品產率及降低成本，能夠製 導體元件。 ，因為亦具有 應變SiGe層 為以儘可能不 ^長，且隨後立 的惡化抑制在 現P +上覆P結 的自動摻雜等 力高，利用該 法（例如FT-IR 111定蠢晶S i層 亦即，在遙晶 成過程中，能 磨；Chemical 又，也能夠利 圓基板的背面 於前述晶圓中 0作為Si蝕刻 氣能力高，且 有效地利用於 程中，進而能 造高品質的半 14 200845142 又，使用上述磊晶矽晶圓作為接合晶圓或基體晶圓， 若藉由晶圓貼合方法來製造SOI晶圓時，基於上述理由， 能夠製造高品質的S0I晶圓。例如將上述的磊晶晶圓作為 接合晶圓使用時，能夠將高品質的磊晶層作為s〇I層。^ 而且，作為用以達成與上述的磊晶矽晶圓同樣效果之 磊晶矽晶圓的結構，亦可以是在矽（Ρ·)基板i上，依照順 序層積P +層4、應變SiGe層2、Si保護層3、磊晶Si層5 而成之構成（第1圖（b))，亦可以是在矽基板1上，依照顺 序層積卩+層4、應變8丨〇6層2、8丨保護層3、？ +層4、蟲 晶Si層5而成之構成（第1圖（c))。如此進行，能夠按照目 的改變P +層的位置或數目。例如為了強化磊晶Si層的吸 氣能力，以如第1圖（a)之類型為佳，顧慮來自基板的污染 時，以第1圖（b)的類型為佳。若是需要更強化吸氣能力 時，能夠製成如第1圖（c)的類型。 為了製造如第1圖（b)、（c)的類型之磊晶晶圓，可以先 準備矽基板1，只要在形成上述應變SiGe層2的製程之 〇 前，進行使上述P +層4磊晶成長之製程即可。 以下，更具體地說明本發明的實驗例。 (實驗1) 〈應變SiGe層的Ge濃度與霧度的關係及si保護層的有效 性> 準備依照CZ法所製造的面方位為{1〇〇}之ρ· (p型高 電阻矽單結晶）基板1(第2圖）。接著，將該p-基板1使用 15 200845142 單片式CVD裝置並在Η:環境、80托（約llkPa)減壓條件， 進行1100°C的H2烘烤。隨後，降溫至69(TC，並在ρ·基 板 1 上，以 SiH4 : 150sccm、GeH4 : 10、40、80sccms 的 各自條件’形成Ge濃度為7.5%、9.1%、12.3%的應變siGe 層2(第2圖）。接著，只有停止GeH4氣體並形成u奈米 的Si保護層3(第2圖），此時，對各Ge濃度的試樣，測 定霧度水準時，任一者都是〇.25ppm左右，是良好的（第3 圖上段^形成Si保護層3後，停止SiH4氣體，並在h2 環境升溫至l〇80°C，以DSC : 45〇SCcm成長約i微米的磊 晶Si層5 (第2圖）。得知此時晶圓的霧度水準，是如第3 圖下段所示，其Ge濃度變高而成為9」、12·3%，霧度水 準惡化，又，Ge濃度為7.5%時，霧度水準是與通常的晶 圓相同程度。 又，Ge濃度7.5%的試樣，若未形成Si保護層3而升 溫至1 08 0°C進行磊晶成長時，確認霧度水準是惡化至無法 測定的程度。如此，清楚知道為了不使應變SiGe層2的表 1) 面粗糙度（霧度）惡化，應變SiGe層2表面的Si保護層3 是非常重要的。 (實驗2) <應變SiGe層的厚度與霧度的關係> 準備依照CZ法所製造的面方位為{100丨之ρ· (p型高 電阻矽單結晶）基板1(第2圖）。接著，將該p-基板〗使用 單片式CVD裝置並在H2環境、80托（約llkPa)減壓條件， 16 200845142 進行1100°c的H2烘烤。隨後，降溫至69(rc，並在p•基 板1上，以SiH4: 15〇Sccm、GeH4: 1〇_削的條件將 Ge濃度設為7.5%，來形成各自各厚度為38奈米、76奈米、The growth temperature of the Ge layer is 750 ° C or less for the purpose of misalignment. When SiH4, Si2H6, D(:S, Si source gas, and GeH4 and GeCl4 are used as the Ge source gas to shape the strained SiGe layer, since any of the above gases are commonly used, ~ m ^ is easy to handle, and has an easy management. The condition for forming the above-mentioned Q · know % Si protective layer is to form the strained SiGe layer with n and μ ue n except for stopping the supply of the source gas. The conditions are the same. The τ 丨 藉 藉 如此 如此 如此 如此 . 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The suppression is minimal. The above-mentioned returning Si layer is preferably p + layer. ^ When attacking the concentration Si layer is P + layer, because of the ability to guarantee the absorbing ability, the usual optical is 13⁄4 The method can measure the diameter direction of the wafer; εδ曰曰 thickness “can improve the film thickness management or product of the epitaxial layer. 筲 Guaranteedly, the present invention provides a method for manufacturing a semiconductor device, characterized in that: Create a half using the insane crystal wafer of the invention #^ The manufacturing method of the device of claim 9, 200845142 has at least a process of forming an element on the wafer wafer and a process of thinning the wafer on which the element is formed; in the thinning process, the above-mentioned high is used Concentrating the Si layer and managing the wafer thickness by optical means, and/or using the strained siGe layer of the above-described stupid wafer to perform the residual stop. As described above, the stray crystal wafer of the present invention is high. Inhalation capability, and because the high-rolling Si layer is used, the wafer can be easily measured by optical means, and the thickness can be easily thinned after the element is formed. In the thinning process, the strained siGe layer is used as the stop layer. Thus, when the stray crystal wafer of the present invention is used for a semiconductor element, not only the gettering capability is high, but also various processes for manufacturing components and wafers are performed. In addition, it can be effectively utilized, which can contribute to an increase in product yield and a reduction in cost. In this case, the above optical method is preferably FT-IR. Thus, 'using FT-IR (Fourier transform infrared light) In the F〇urier 〇Transform Infrared Spectroscopy method, the epitaxial thickness can be accurately measured in a simple and non-contact manner, and the quality management of the epitaxial wafer of the product becomes possible. Moreover, the present invention provides a manufacturing method. The method of manufacturing a wafer is to use the above-described method for manufacturing an epitaxial wafer of the present invention, wherein the epitaxial wafer is used as a bonding wafer or a base wafer and is crystallized. The round-fit method is used to fabricate an SOI wafer. Since the epitaxial germanium wafer of the present invention has the above advantages, it is used as a bonding wafer (wafer for forming an SOI layer) or a substrate wafer for use as 200844142 (for When the wafer of the SOI layer is supported, high-quality wafers can be manufactured at a low cost. Since the epitaxial germanium wafer of the present invention has a high-concentration layer of one layer or two layers as an inhalation portion, its gettering ability is higher than that of a usual wafer having only a strain layer. In addition, since the high-concentration Si layer can easily measure and monitor the film thickness distribution of the stray layer of the diameter of the wafer by optical means such as FT-IR, the film thickness management and quality assurance of the layer can be easily and accurately performed. Moreover, the degree of the process of the component process can be simplified, and it can also be utilized in the component formation process to contribute to the improvement of the yield of the product and the cost reduction. Further, in the method of manufacturing an epitaxial germanium wafer according to the present invention, it is possible to greatly reduce the incorporation of impurities such as automatic doping during growth, as compared with the method of manufacturing a P-coated epitaxial wafer. Further, by forming the Si protective layer immediately after the formation of the SiGe layer, the deterioration of the strain SiGe layer roughness (haze) can be minimized, and finally, the epitaxial wafer having excellent properties can be obtained. Further, the semiconductor element is manufactured by using the epitaxial germanium wafer of the present invention. Since a high-concentration Si layer is used, the thickness distribution of the epitaxial layer can be easily measured by optical means by non-contact, so that the element region is formed on the back side. When thinning processes, etc., wafer thickness management and wafer quality management can be easily performed. Further, since the strained SiGe layer can be used as a stop layer, it is possible to prevent surface roughness due to etching during the component process. With the SOI degree Si SiGe by the direction of the stupid film thickness of the thin P + on the shame strain table flat, after the mode, the tube is in the middle of the table 11 200845142 so when using the above-mentioned epitaxial wafer, not It is only a high-suction capability, and it can also effectively utilize the ® and the use of the epitaxial wafer of the present invention as a bonding wafer or substrate of the S 01 wafer in various processes of component and wafer fabrication. When a wafer is fabricated and a SOI wafer is fabricated by wafer bonding, a high-quality S〇I wafer can be manufactured because of the above characteristics. [Embodiment] Hereinafter, the embodiment of the present invention will be specifically described with reference to the drawings, but the present invention is not limited to these descriptions. Fig. 1 is a schematic view of an epitaxial germanium wafer according to the present invention. (a) - respectively show three aspects of the present invention. As a representative example of the three aspects of the present invention, a method of manufacturing the epitaxial wafer shown in Fig. 1(a) will be described below, but the first (b) and (c) are essentially the same as (a). The manufacturing method has not changed. In the present embodiment, a p-type high resistance (low doping concentration) substrate (hereinafter referred to as a P-substrate) is used in order to avoid the problem of cost increase and automatic doping. Further, the method of producing the P substrate, the plane orientation, and the like are not particularly limited as long as they are appropriately selected in accordance with the purpose. For example, it is usually manufactured according to the CZ (Czochralski) method or the FZ (Floating Zone) method. Next, the strained SiGe layer 2 is subjected to epitaxial growth on the substrate 1, and the pretreatment is to remove the natural ruthenium oxide on the surface of the p-substrate 1 on the surface of 200845142 in an H2 environment of about 11 〇〇t: (not shown) Then, the temperature is lowered to 75 〇t: the following, and the strained SiGe layer 2 is grown in a Ge inferiority which does not cause a bad dislocation (differential row), preferably at a concentration of less than 1%. In this case, as the Si source gas, any one of 81114, 812116, 0€8 (dioxane) and 11 (:3 (trioxane) is preferably used as the Ge source gas, and the use of ^... and GeCU2 is used. Next, the Si protective film 3 is laminated on the strained SiGe layer 2. The layering of the Si protective film 3 is preferably such that only the Ge source gas is shielded after the epitaxial growth of the strained SiGe layer 2 is completed. The conditions for maintaining this state are continuously increased. This is because the Si protective layer 3 is for preventing the surface roughness of the strained SiGe layer 2 from deteriorating during the temperature rise for performing the stray crystal growth of the p + layer 4. Therefore, it is important to form the strained SiGe layer 2 immediately after it is formed. After the S1 protective layer 3 is formed, the temperature is raised to a predetermined temperature, and the acceptor impurity is doped at a high concentration (adjusted to a desired resistivity). The si layer, that is, the epitaxial growth of the P + layer 4. At this time, as the acceptor impurity, B (boron) is usually used, but other dopants such as Ga (gallium) may be used. Finally, in P + On layer 4, the temperature is adjusted to a desired resistivity at a predetermined temperature to form a high The resist (low concentration) epitaxial Si layer 5 is thus obtained, and a structure having a low concentration (high resistance) Si layer on a high concentration (low resistance) Si layer, that is, a P + overlying p structure can be obtained. The epitaxial germanium wafer of the present invention has a gettering site at the interface between the strained SiGe layer and the Si layer directly contacting the upper and lower layers because it is not only the strained SiGe layer but also has a high concentration si layer (gettering 13 200845142 site). At the same time, if the gettering ability (aggregation ability) of Fe or the like is used in the high-concentration Si layer, for example, when b is used, it is possible to obtain a substance having a high gas absorption capability as compared with the case of a single layer, which is caused by the condition of occurrence of poor dislocation. Since the crystal W layer is laminated with the Si protective layer, the surface roughness thereof can be minimized. The present invention is capable of suppressing the element region caused by the impurity by the & crystal layer and the 'comparation with the previous case'. Deterioration of characteristics. In the case of the above-mentioned silly crystal wafer, not only the surface concentration Si layer in the gettering wafer, but also by a simple optical method, can be accurately measured in a non-contact manner. Film thickness, This quality management can be made easy. Management of the epitaxial layer of the wafer, or film thickness management in subsequent fabrication of components such as dry-type or CMP (Mechanical Polish). For: by lapping The thickness of the crystal after the element was produced was measured to reduce the thickness. Further, the internal strain S i G e layer ' can also be used as a stop layer in the thinning process. Thus, the insect crystal wafer of the present invention not only absorbs not only can be effectively utilized for manufacturing epitaxial wafers, but also can form various kinds of subsequent components to wafer fabrication to help improve product production. Rate and cost reduction, the ability to make conductor components. Because the strained SiGe layer is also as low as possible, and the subsequent deterioration suppresses the high doping force of the P+ overlying P-junction, and the method is used (for example, FT-IR 111 determines the stray crystal S). The i layer, that is, in the process of the remote crystal formation, can be ground; the chemical layer can also be used in the back surface of the substrate to have a high ability to etch the gas as 0 in the wafer, and can be effectively utilized in the process, thereby making the height high. Quality Half 14 200845142 In addition, when the above-mentioned epitaxial wafer is used as a bonding wafer or a base wafer, when a SOI wafer is manufactured by a wafer bonding method, a high-quality SOI wafer can be manufactured for the above reasons. For example, when the epitaxial wafer described above is used as a bonding wafer, a high-quality epitaxial layer can be used as the s〇I layer. Moreover, as an epitaxial layer for achieving the same effect as the above-described epitaxial wafer. The structure of the germanium wafer may be formed by laminating a P + layer 4, a strained SiGe layer 2, a Si protective layer 3, and an epitaxial Si layer 5 on a substrate (i). Figure (b)), also on the ruthenium substrate 1, layering 卩+layer 4, strain 8 in order 〇 6 layers 2, 8 丨 protective layer 3, ? + layer 4, insect crystal Si layer 5 (Fig. 1 (c)). In this way, the position or number of P + layers can be changed according to the purpose. In order to enhance the gettering ability of the epitaxial Si layer, it is preferable to use the type as shown in Fig. 1(a), and it is preferable to use the type of Fig. 1(b) when it is concerned with contamination from the substrate. If it is necessary to enhance the gettering ability In the case of the epitaxial wafer of the type shown in Fig. 1 (b), (c), the germanium substrate 1 may be prepared first, as long as the strained SiGe layer is formed. The process of epitaxial growth of the P + layer 4 may be performed before the process of 2. The experimental example of the present invention will be more specifically described below. (Experiment 1) <Relationship between Ge concentration and haze of strained SiGe layer And the effectiveness of the si protective layer> The ρ· (p-type high resistance tantalum single crystal) substrate 1 (Fig. 2) prepared by the CZ method having a plane orientation of {1〇〇} is prepared. Next, the p- The substrate 1 was subjected to H2 baking at 1100 ° C using a 15 200845142 monolithic CVD apparatus under reduced pressure in an environment of 80 Torr (about ll kPa). Subsequently, the temperature was lowered to 69 (TC). On the ρ·substrate 1, a strained siGe layer 2 having a Ge concentration of 7.5%, 9.1%, and 12.3% was formed under the respective conditions of SiH4: 150 sccm and GeH4: 10, 40, and 80 sccms (Fig. 2). Only the Si protective layer 3 (Fig. 2) in which the GeH4 gas is stopped and the u nanon is formed. In this case, when the haze level is measured for each of the Ge concentration samples, either of them is about 25 ppm, which is good. (Fig. 3, upper part ^ After forming Si protective layer 3, stop SiH4 gas, and raise the temperature to l〇80 °C in h2 environment, and grow epitaxial Si layer 5 of about i micron in DSC: 45〇SCcm (Fig. 2) . The haze level of the wafer at this time is as shown in the lower part of Fig. 3, and the Ge concentration is increased to 9" and 12·3%, the haze level is deteriorated, and the Ge concentration is 7.5%. The level is the same as the normal wafer. Further, when the Si protective layer 3 was not formed and the temperature was raised to 1800 °C to carry out epitaxial growth, it was confirmed that the haze level deteriorated to such an extent that it could not be measured. Thus, it is clear that the Si protective layer 3 on the surface of the strained SiGe layer 2 is very important in order not to deteriorate the surface roughness (haze) of the strained SiGe layer 2. (Experiment 2) <Relationship between thickness of strained SiGe layer and haze> Preparation of a surface orientation of {100 Å (p-type high resistance 矽 single crystal) substrate 1 manufactured by the CZ method (Fig. 2) . Next, this p-substrate was subjected to H2 baking at 1,100 ° C in a H 2 atmosphere, a decompression condition of 80 Torr (about 11 kPa), and 16 200845142 using a monolithic CVD apparatus. Subsequently, the temperature was lowered to 69 (rc, and on the p• substrate 1, the Ge concentration was set to 7.5% under conditions of SiH4: 15 〇 Sccm, GeH4: 1 〇 _, to form respective thicknesses of 38 nm, 76. Nano,
!52奈米之應變SiGe層2(第2圖）。接著，只有停止 氣體並形成18奈米的Si保護層3(第2圖），此時各厚度的 應變SiGe層2的霧度水準任一者都是〇 25ppm左右，是 良好的（第4圖上段接著，在形成Si保護層3後，停止 SiH4氣體，並在h2環境升溫至1〇8〇。〇，以DsC: 45〇scem 成長約1微米的磊晶Si層5。測定此時晶圓的霧度水準之 結果，得知在Ge濃度為7.5%的條件下，應變層2 的厚度至152奈米為止，未觀察到磊晶成長後的磊晶si 層5的霧度水準的惡化，是與通常的晶圓相同程度（第4 圖下段）。 第3圖下段的Ge濃度為9·1%的試樣，即便其應變“以 層2的厚度為128奈米，霧度亦開始有部分性惡化的傾向， 為了在蠢晶S1層5成長後亦能夠擔保良好的霧度水準，推 測Ge濃度再高亦必須抑制在1 〇%以下。 (實驗3) <依照FT-IR法測定使用P +層之晶圓直徑方向的磊晶厚度 分布> 準備依照CZ法所製造的面方位為{100}之p- (p型高 電阻發單結晶）基板1(第5圖（a))。接著，將該p-基板1使 用單片式CVD裝置並在I環境、80托減壓條件，進行11〇〇 17 200845142 °C的H2烘烤。隨後，降溫至1 000°C，並在p-基板i上， 以 DCS : 200sccm、100ppmB2H6 : 170sccm 的條件，夢由 調整時間，來將P +層4(電阻率為0·01 Ω cm)各自形成〇 25 微米、0.5微米、1.0微米（第5圖（a))。接著，在p +層4上， 以1 080°C、DSC : 450sccm成長約5微米的磊晶Si層5(電 阻率為10 Ω cm)。使用光學手法（FT-IR法）測定如此進行所 得到各試樣的晶圓直徑方向的磊晶Si層5的膜厚度分布 (第5圖（b))。將在P +矽基板上以同一條件使Si層成長後 的試樣作為參考時，在P_基板1使P +層4成長1微米而得 的試樣，顯示大致同樣的值，〇·5微米的試樣是顯示低一 些的值，0.25微米的試樣則無法測定。 從如此進行所得到的結果，得知P +層4為1微米左右 時，藉由通常的光學手法能夠精確度良好地進行磊晶厚度 測定，又，在P +層4為0.5微米時亦能夠充分地監控。又， 本次的測定條件雖然無法計測〇. 2 5微米的試樣，但是藉由 改變測定條件，仍相當具有能狗測定的可能性。 (實驗4) <B(硼）的深度方向的分布曲線及依照CV法測定晶圓的電 阻率> 在本實驗例，是使用在實驗3中所使用的其P +層4為 1微米的試樣。藉由SIMS(二次離子質譜法；Secondary Ion Mass Spectrometer)測定該試樣的晶圓中心部及邊緣部之 B濃度的深度方向的分布曲線（第6圖（b))，並藉由CV(電 18 200845142 谷電壓；Capacitance Voltage)法測定在中 β R/2 口ρ 及 邊緣部之5微米的Ρ·蠢晶Si層5的電I1且率（第7圖）。 依照FT-IR法所測定的晶圓厚度（中心部為4·38微 米、邊緣部為4.69微米）是如SIMS測定結果所示’是相當 於B濃度為5xl〇i8/立方公分，顯示比該濃度低時無法藉由 FT-IR法測定。亦即，為了形成p +層，使用B作為受體不 純物時，至少必須5 X 1 〇 1 8 /立方公分以上的濃度（參照第 广' 6(a)、（b)所示之各箭號）。又，如第7圖所示，得知本試樣 時亦此夠良好地進行cv測定，在製造蠢晶時’ p基板上 的p蠢晶晶圓亦能夠使用作為測定磊晶厚度及測定電阻 率之監控晶圓。 從實驗1至實驗4所得到的結果，得知本發明之磊晶 矽晶圓，其應變SiGe層的Ge濃度以10〇/〇以下為佳，又， 在形成應變SiGe層後，若立刻形成si保護層，在抑制表 面粗糙度的惡化方面，是重要的。而且，藉由良好地活用 兩濃度Sl層，可使用光學手法簡便地測定晶圓直徑方向的 Ο 磊晶厚度。此時，作為光學手法，例如使用FT-IR法時， 便能夠簡便且精確度良好地測定磊晶厚度。$外，使用 FT-IR法來測定膜厚度時，較佳是使p +層比〇·25微米厚， Ρ層的遙晶厚度若& . ^ s ηΛΤ 為1微左右時，因為磊晶厚度測定及cv 測定能夠得到斑P + # f - ’、 基板時同樣的結果，顯示充分地此夠代 替P +基板。 以下 顯示本發 明的實施例來具體地說明，但是本發 19 200845142 明未限定於下述的實施例。 (實施例1、2、3) 如以下進行，來製造具有如第1圖（a)所示結構之磊晶 發晶圓。 首先，準備依照CZ法所製造的面方位為{100}之p- (P 型高電阻矽單結晶）基板1。接著，將該基板1使用單片 式CVD裝置並在Η2環境、80托（約llkPa)減壓條件，進 行1100°C的H2烘烤。隨後，降溫至690°C，並在p-基板1 上，以 SiH4 : 150sccm、GeH4 : lOsccms 的條件，形成 Ge 濃度為7.5%的應變SiGe層2。接著，只有停止GeH4氣體 並形成18奈米的Si保護層3。隨後，升溫至1〇〇〇°C，在!52 nanometer strain SiGe layer 2 (Fig. 2). Next, only the gas is stopped and the 18 nm Si protective layer 3 is formed (Fig. 2). At this time, the haze level of the strained SiGe layer 2 of each thickness is about 25 ppm, which is good (Fig. 4). In the upper stage, after the Si protective layer 3 is formed, the SiH4 gas is stopped, and the temperature is raised to 1 〇 8 在 in the h2 environment. 〇, the epitaxial Si layer 5 of about 1 μm is grown by DsC: 45 〇 scem. As a result of the haze level, it was found that the thickness of the strained layer 2 was 152 nm under the condition of a Ge concentration of 7.5%, and the deterioration of the haze level of the epitaxial Si layer 5 after the epitaxial growth was not observed. It is the same level as a normal wafer (the lower part of Fig. 4). The sample with a Ge concentration of 9.1% in the lower part of Fig. 3, even if the strain is "the thickness of layer 2 is 128 nm, the haze starts to have The tendency to partially deteriorate, in order to ensure a good haze level after the growth of the S1 layer 5, it is estimated that the Ge concentration must be suppressed to be less than 1%. (Experiment 3) <Measured by FT-IR method Epitaxial thickness distribution in the diameter direction of the wafer using the P + layer > Preparing p- (p-type) having a plane orientation of {100} according to the CZ method High-resistance single crystal) substrate 1 (Fig. 5 (a)). Next, the p-substrate 1 was subjected to a single-chip CVD apparatus and subjected to a reduced pressure of 80 Torr at a temperature of 80 45 17 200845142 °C. H2 baking. Subsequently, the temperature is lowered to 1 000 ° C, and on the p-substrate i, with DCS: 200 sccm, 100 ppm B2H6: 170 sccm, the dream is adjusted by time to P + layer 4 (resistivity is 0. 01 Ω cm) is formed by 〇25 μm, 0.5 μm, and 1.0 μm (Fig. 5 (a)). Next, epitaxial Si of about 5 μm is grown at 1 080 ° C, DSC: 450 sccm on p + layer 4. Layer 5 (resistivity: 10 Ω cm). The film thickness distribution of the epitaxial Si layer 5 in the wafer diameter direction of each sample thus obtained was measured by an optical method (FT-IR method) (Fig. 5(b) When a sample in which the Si layer was grown under the same conditions on the P + germanium substrate was used as a reference, the sample obtained by growing the P + layer 4 by 1 μm on the P_ substrate 1 showed substantially the same value. The sample of 5 μm shows a lower value, and the sample of 0.25 μm cannot be measured. From the results obtained in this way, it is found that the P + layer 4 is about 1 μm, by the usual The method of measuring the thickness of the epitaxial layer can be accurately measured, and can be sufficiently monitored even when the P + layer 4 is 0.5 μm. Moreover, although the measurement conditions of this time cannot be measured, the sample of 2 5 μm cannot be measured. By changing the measurement conditions, it is still quite possible to measure the dog. (Experiment 4) <B (boron) in the depth direction distribution curve and the resistivity of the wafer according to the CV method> In this experimental example, A sample having a P + layer 4 of 1 μm used in Experiment 3 was used. The distribution curve of the B concentration in the center and edge portions of the wafer of the sample was measured by SIMS (Secondary Ion Mass Spectrometer) (Fig. 6(b)), and by CV ( Electric 18 200845142 Valley voltage; Capacitance Voltage method was used to measure the electric I1 ratio of the 5 μm Ρ·Silicon Si layer 5 in the middle β R/2 port ρ and the edge portion (Fig. 7). The thickness of the wafer measured by the FT-IR method (the center portion is 4.38 micrometers and the edge portion is 4.69 micrometers) is as shown by the SIMS measurement result, which is equivalent to the B concentration of 5 x l 〇 i 8 /cm ^ 3 , which is When the concentration is low, it cannot be measured by the FT-IR method. That is, in order to form the p + layer, when B is used as the acceptor impurity, it must have a concentration of at least 5 X 1 〇18 /cm 3 or more (refer to the arrows indicated by the general '6(a), (b) ). Further, as shown in Fig. 7, the cv measurement was performed well enough when the sample was obtained, and the p-crystal wafer on the p-substrate could be used as the measurement of the epitaxial thickness and the measurement resistance in the production of the stray crystal. Rate monitoring wafers. From the results obtained in Experiment 1 to Experiment 4, it was found that the epitaxial germanium wafer of the present invention has a Ge concentration of 10 Å/〇 or less in the strained SiGe layer, and is formed immediately after forming the strained SiGe layer. The si protective layer is important in suppressing deterioration of surface roughness. Further, by well utilizing the two-concentration S1 layer, the 磊 epitaxial thickness in the wafer diameter direction can be easily measured by an optical technique. In this case, when the FT-IR method is used as an optical method, the epitaxial thickness can be measured easily and accurately. In addition, when the film thickness is measured by the FT-IR method, it is preferable to make the p + layer thicker than 〇·25 μm, and the thickness of the crystallization layer of the ruthenium layer is & . ^ s η ΛΤ is about 1 micrometer because of epitaxy Thickness measurement and cv measurement The same results as in the case of obtaining the spot P + # f - ', and the substrate showed that it was sufficient to replace the P + substrate. The embodiment of the present invention will be specifically described below, but the present invention is not limited to the following embodiments. (Examples 1, 2, and 3) An epitaxial wafer having a structure as shown in Fig. 1(a) was produced as follows. First, a p- (P-type high resistance tantalum single crystal) substrate 1 having a plane orientation of {100} manufactured by the CZ method is prepared. Next, the substrate 1 was subjected to H2 baking at 1,100 °C using a monolithic CVD apparatus under reduced pressure in a Η2 atmosphere at 80 Torr (about ll kPa). Subsequently, the temperature was lowered to 690 ° C, and a strained SiGe layer 2 having a Ge concentration of 7.5% was formed on the p-substrate 1 under the conditions of SiH4 : 150 sccm and GeH 4 : 10 sccms. Next, only the GeH4 gas was stopped and a 18 nm Si protective layer 3 was formed. Then, heat up to 1 ° ° C, at
Si 保護層 3 上，以 DSC : 200sccm、100ppmB2H6 : 1 70sccm 的條件，並藉由調整時間來形成1·〇微米P +層4(電阻率為 O.OlQcm)。而且，以 1080°C、DSC: 450sccm 在 P +層 4 上成長5微米的蠢晶Si層5(電阻率為lOncm)’來得到最 後的磊晶矽晶圓（實施例1)。 如以下進行，來製造具有如第1圖（b)所示結構之磊晶 梦晶圓。 首先，準備依照CZ法所製造的面方位為{100}之p- (p 型高電阻矽單結晶）基板1 ^接著，將該P-基板1使用單片 式CVD裝置並在H2環境、80托（約1 lkPa)減壓條件，進 行110(TC的Hi烘烤。隨後，降溫至1〇〇〇。(：，並在p-基板 1 上，以 DSC : 20 0sccm、100ppmB2H6 ·· 170sccm 的條件， 並藉由調整時間來形成1.0微米P +層4(電阻率為〇.〇1Ω 20 200845142 cm)。隨後，降溫至690°C，並在P +層4上，以SiH4 : 15 0sccm、GeH4 : lOsccms的條件，形成Ge濃度為7 5%的 應變SiGe層2。接著，只有停止GeH4氣體並形成u奈米 的Si保護層3。而且，在Si保護層3上，以1080 °C、DSC: 45 Osccm在P +層4上成長5微米的磊晶Si層5(電阻率為 10 Ω cm)，來得到最後的磊晶矽晶圓（實施例2)。 又，如下進行，來製造具有如第1圖（c)所示結構之磊 f4 晶矽晶圓。 首先，依照與實施例2同樣的製程，進行至形成si 保護層3為止。隨後，升溫至1〇〇(TC，在Si保護層3上， 以 DSC: 200sccm、100ppmB2H6: 170sccm 的條件，並藉 由調整時間再次形成1.0微米P +層4(電阻率為0.01Ω cm)。而且，在該 P +層 4 上，以 1080°C、DSC : 450sccm 成長5微米的磊晶Si層5(電阻率為10 Ω cm)，來得到最後 的磊晶矽晶圓（實施例3)。 實施例1、2、3所製造的磊晶矽晶圓的磊晶Si層5 Q 的霧度，是各自如第8圖（a)、（b)、（C)所示。任一者的霧 度都是0.26ppm，是良好的。 又，使用光學手法（FT-IR法）測定在實施例 1、2、3 所製造的磊晶矽晶圓的晶圓直徑方向的磊晶Si層5之膜厚 度分布。結果如第9圖的（a)、（b)、（c)所示。因為P +層的 存在，所以能夠測定磊晶Si層5的膜厚度分布。 又，本發明之實施例1的磊晶矽晶圓的吸氣能力是如 以下進行評價。 21 200845142 首先，作為參考用磊晶晶圓，是如第10圖（a)、（b)所 示，亦即製造在P +基板上成長磊晶Si層而成之磊晶晶圓 作為參考1，並製造從實施例1的晶圓除去P +層4而成之 蠢晶晶圓作為參考2。又，參考1及參考2的磊晶晶圓的 各層的成長條件是依據實施例。 在實施例1的磊晶晶圓、參考1及2的磊晶晶圓的各 晶圓表面，將Ni及Fe以约5xl012atoms/cm2的濃度塗布， 並藉由熱處理1小時來使其擴散至内部。接著，蝕刻表面 附近的Si層，並使用ICP-MS來測定該溶液中的Ni及Fe 濃度。各晶圓表面的金屬濃度是如表1所示。 [表1] 參考1 參考2 實施例1 Ni 濃度（atoms/cm2) 2xl012 5xl010 lxlO10 Fe 濃度（atoms/cm2) lxlO10 5x10" 2xl010 參考1之在P +基板上成長磊晶Si層而成之磊晶晶圓， 雖然對Fe具有吸氣能力，但是對Ni則未觀察到有吸氣能 U 力。參考2之未形成P層的晶圓，雖然由於應變siGe層2, 對Ni具有吸氣能力，但是因為無p +層，所以對Fe的吸氣 能力低。另一方面，得知實施例的晶圓對Ni、Fe雙方都具 有高吸氣能力。 又，本發明未限定於上述實施形態。上述實施形態是 例示性，凡是具有與本發明之申請專利範圍所記載之技術 思想實質上相同構成、且達成相同作用效果之物，無論如 何都包含在本發明的技術範圍内。 22 200845142 【圖式簡單說明】 第1圖（a )〜（c )都是表示本發明的磊晶矽晶圓的結構 之概略圖。 第2圖是表示在實驗1及2中的磊晶矽晶圓的結構之 概略圖。 第3圖是表示應變SiGe層的Ge濃度及厚度與霧度的 關係之圖（實施例1)。On the Si protective layer 3, a DSC: 200 sccm, 100 ppm B2H6: 1 70 sccm was used, and a 1 〇 micron P + layer 4 (resistivity O.OlQcm) was formed by adjusting the time. Further, a stray Si layer 5 (resistivity: lOncm) of 5 μm was grown on the P + layer 4 at 1080 ° C and DSC: 450 sccm to obtain a final epitaxial germanium wafer (Example 1). An epitaxial wafer having the structure shown in Fig. 1(b) was produced as follows. First, a p- (p-type high resistance tantalum single crystal) substrate 1 having a plane orientation of {100} manufactured in accordance with the CZ method is prepared. Next, the P-substrate 1 is used in a single-chip CVD apparatus and in an H2 environment, 80. Under pressure (about 1 lkPa) under reduced pressure, perform 110 (Hi baking of TC. Then, cool down to 1 〇〇〇. (:, and on p-substrate 1, with DSC: 20 0sccm, 100ppmB2H6 · · 170sccm Conditions, and by adjusting the time to form a 1.0 micron P + layer 4 (resistivity 〇.〇1Ω 20 200845142 cm). Subsequently, the temperature is lowered to 690 ° C, and on the P + layer 4, SiH4 : 15 0 sccm, GeH4 : conditions of lOsccms, forming a strained SiGe layer 2 having a Ge concentration of 75%. Then, only the Si protective layer 3 of the Ge nanometer gas is stopped and formed of u nano. Moreover, on the Si protective layer 3, at 1080 ° C, DSC: 45 Osccm A 5 micron epitaxial Si layer 5 (resistivity 10 Ω cm) was grown on the P + layer 4 to obtain a final epitaxial germanium wafer (Example 2). The epitaxial f4 wafer wafer having the structure shown in Fig. 1(c) is first formed in the same manner as in the second embodiment until the formation of the si protective layer 3. 1 〇〇 (TC, on the Si protective layer 3, with DSC: 200 sccm, 100 ppm B2H6: 170 sccm, and again forming 1.0 μm P + layer 4 (resistivity 0.01 Ω cm) by adjusting the time. On the P + layer 4, a 5 μm epitaxial Si layer 5 (resistivity: 10 Ω cm) was grown at 1080 ° C and DSC: 450 sccm to obtain a final epitaxial germanium wafer (Example 3). The haze of the epitaxial Si layer 5 Q of the epitaxial germanium wafer manufactured by 2, 3 is as shown in Fig. 8 (a), (b), and (C), respectively. It was 0.26 ppm, which was good. Further, the film thickness of the epitaxial Si layer 5 in the wafer diameter direction of the epitaxial wafers produced in Examples 1, 2, and 3 was measured by an optical method (FT-IR method). The results are shown in (a), (b), and (c) of Fig. 9. Because of the presence of the P + layer, the film thickness distribution of the epitaxial Si layer 5 can be measured. The gettering ability of the epitaxial wafer is evaluated as follows. 21 200845142 First, the epitaxial wafer is used as a reference, as shown in Fig. 10 (a) and (b), that is, on a P + substrate. Growth epitaxial Si The epitaxial wafer was formed as reference 1, and the amorphous wafer obtained by removing the P + layer 4 from the wafer of Example 1 was fabricated as reference 2. Further, the layers of the epitaxial wafer of Reference 1 and Reference 2 were used. The growth conditions are based on the examples. Ni and Fe were applied at a concentration of about 5×10 12 atoms/cm 2 on the surface of each wafer of the epitaxial wafer of Example 1 and the epitaxial wafers of References 1 and 2, and were diffused to the inside by heat treatment for 1 hour. . Next, the Si layer near the surface was etched, and the concentrations of Ni and Fe in the solution were measured by ICP-MS. The metal concentration of each wafer surface is as shown in Table 1. [Table 1] Reference 1 Reference 2 Example 1 Ni concentration (atoms/cm2) 2xl012 5xl010 lxlO10 Fe concentration (atoms/cm2) lxlO10 5x10" 2xl010 Reference 1 The epitaxial layer formed by growing an epitaxial Si layer on a P + substrate The wafer, although having a gettering ability for Fe, did not observe an inspiratory U force for Ni. Referring to the wafer in which the P layer is not formed, although the SiGe layer 2 has a gettering ability for Ni, since there is no p + layer, the gettering ability to Fe is low. On the other hand, it is known that the wafer of the embodiment has a high gas absorption capability for both Ni and Fe. Further, the present invention is not limited to the above embodiment. The above-described embodiments are exemplified, and any object having substantially the same configuration as the technical idea described in the patent application scope of the present invention and achieving the same operational effects is included in the technical scope of the present invention. 22 200845142 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (a) to (c) are schematic views showing the structure of an epitaxial germanium wafer of the present invention. Fig. 2 is a schematic view showing the structure of the epitaxial wafer in Experiments 1 and 2. Fig. 3 is a view showing the relationship between the Ge concentration and the thickness of the strained SiGe layer and the haze (Example 1).
第4圖是表示使應變SiGe層的Ge濃度為一定時之應 變SiGe層的厚度與霧度的關係之圖（實施例2)。 第5圖（a)是表示在實驗3中的蠢晶石夕晶圓的結構之概 略圖；（b)是表示依照FT-IR法之晶圓直徑方向的磊晶厚度 分布測定結果之圖（實驗3)。 第6圖是表示依照FT- IR法所測定的磊晶厚度分布圖 (a )、與測定B之深度方向的分布曲線的結果（b)之關聯性 之圖（實驗4)。 第7圖是表示測定實驗4中的磊晶矽晶圓的P —基板的 C-V電阻率的結果之圖。 第8圖是表示磊晶S i層表面的霧度之圖；（a )實施例 1、（b)實施例2、（c)實施例3。 第9圖是表示依照FT-IR法之晶圓直徑方向的磊晶厚 度分布測定結果之圖。 第1 0圖是表示評價吸氣能力時所使用的參考用磊晶 矽晶圓的結構之概略圖，（a)是使磊晶Si層在P +基板上成 23 200845142 的晶圓除去P +層 長而成的磊晶矽晶圓，（b )是從實施例1 後的蠢晶砍晶圓。 【主要元件符號說明】 1 P_基板 2 應 3 Si保護層 4 P + 5 磊晶Si層 變 SiGe 層Fig. 4 is a view showing the relationship between the thickness of the strained SiGe layer and the haze when the Ge concentration of the strained SiGe layer is constant (Example 2). Fig. 5(a) is a schematic view showing the structure of the smectite wafer in the experiment 3, and Fig. 5(b) is a view showing the measurement results of the epitaxial thickness distribution in the wafer diameter direction according to the FT-IR method ( Experiment 3). Fig. 6 is a graph showing the correlation between the epitaxial thickness distribution map (a) measured by the FT-IR method and the result (b) of the distribution curve in the depth direction of the measurement B (Experiment 4). Fig. 7 is a graph showing the results of measuring the C-V resistivity of the P-substrate of the epitaxial wafer in Experiment 4. Fig. 8 is a view showing the haze of the surface of the epitaxial Si layer; (a) Example 1, (b) Example 2, and (c) Example 3. Fig. 9 is a view showing the results of measurement of the epitaxial thickness distribution in the wafer diameter direction in accordance with the FT-IR method. Fig. 10 is a schematic view showing the structure of a reference epitaxial germanium wafer used for evaluating the gettering ability, and (a) is a wafer in which the epitaxial Si layer is formed on the P + substrate to form 23 200845142. The layered epitaxial wafer, (b) is the wafer cut from the wafer after the first embodiment. [Main component symbol description] 1 P_substrate 2 should be 3 Si protective layer 4 P + 5 epitaxial Si layer change SiGe layer
24twenty four