JP4528659B2 - クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム - Google Patents

クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム Download PDF

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Publication number
JP4528659B2
JP4528659B2 JP2005098512A JP2005098512A JP4528659B2 JP 4528659 B2 JP4528659 B2 JP 4528659B2 JP 2005098512 A JP2005098512 A JP 2005098512A JP 2005098512 A JP2005098512 A JP 2005098512A JP 4528659 B2 JP4528659 B2 JP 4528659B2
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Japan
Prior art keywords
delay time
jitter
supply voltage
clock
calculating
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Japanese (ja)
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JP2006277557A5 (enExample
JP2006277557A (ja
Inventor
孝文 中柴
光子 高田
隆浩 越智
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2005098512A priority Critical patent/JP4528659B2/ja
Priority to US11/392,538 priority patent/US7295938B2/en
Publication of JP2006277557A publication Critical patent/JP2006277557A/ja
Publication of JP2006277557A5 publication Critical patent/JP2006277557A5/ja
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Nonlinear Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2005098512A 2005-03-30 2005-03-30 クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム Expired - Fee Related JP4528659B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005098512A JP4528659B2 (ja) 2005-03-30 2005-03-30 クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム
US11/392,538 US7295938B2 (en) 2005-03-30 2006-03-30 Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005098512A JP4528659B2 (ja) 2005-03-30 2005-03-30 クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム

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JP2006277557A JP2006277557A (ja) 2006-10-12
JP2006277557A5 JP2006277557A5 (enExample) 2007-08-23
JP4528659B2 true JP4528659B2 (ja) 2010-08-18

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JP2005098512A Expired - Fee Related JP4528659B2 (ja) 2005-03-30 2005-03-30 クロックジッタ算出装置、クロックジッタ算出方法、およびクロックジッタ算出プログラム

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US (1) US7295938B2 (enExample)
JP (1) JP4528659B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4769687B2 (ja) * 2006-10-30 2011-09-07 富士通セミコンダクター株式会社 タイミング検証方法、タイミング検証装置及びタイミング検証プログラム
US8134384B2 (en) * 2006-11-08 2012-03-13 Freescale Semiconductor, Inc. Method for testing noise immunity of an integrated circuit and a device having noise immunity testing capabilities
JP2008287666A (ja) * 2007-05-21 2008-11-27 Sharp Corp 回路動作検証装置、半導体集積回路の製造方法、回路動作検証方法、制御プログラムおよび可読記録媒体
US8739099B1 (en) * 2007-07-20 2014-05-27 Altera Corporation Method and apparatus for determining clock uncertainties
JP2009187325A (ja) * 2008-02-06 2009-08-20 Nec Electronics Corp 半導体集積回路の設計方法および設計支援装置
US9565036B2 (en) 2009-06-30 2017-02-07 Rambus Inc. Techniques for adjusting clock signals to compensate for noise
JP2011034480A (ja) 2009-08-05 2011-02-17 Renesas Electronics Corp ジッタ算出装置、ジッタ算出方法、及びジッタ算出プログラム
JP5640259B2 (ja) 2010-06-09 2014-12-17 ルネサスエレクトロニクス株式会社 回路シミュレーション方法および回路シミュレーション装置
US8832616B2 (en) * 2011-03-18 2014-09-09 Sage Software, Inc. Voltage drop effect on static timing analysis for multi-phase sequential circuit
JP6089728B2 (ja) * 2013-01-30 2017-03-08 株式会社ソシオネクスト 半導体装置の設計方法、プログラム及び設計装置
JP2015230543A (ja) 2014-06-04 2015-12-21 株式会社ソシオネクスト 設計装置、設計方法及び設計プログラム
KR102327339B1 (ko) 2015-05-06 2021-11-16 삼성전자주식회사 집적 회로와 이를 포함하는 컴퓨팅 장치

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004077079A1 (ja) * 1993-08-25 2004-09-10 Hitoshi Ujiie ジッタ解析装置
JPH10321725A (ja) 1997-05-14 1998-12-04 Toshiba Corp 半導体集積回路の設計方法及び装置
TW559668B (en) * 1999-02-08 2003-11-01 Advantest Corp Apparatus for and method of measuring a jitter
JP2001084763A (ja) * 1999-09-08 2001-03-30 Mitsubishi Electric Corp クロック発生回路およびそれを具備した半導体記憶装置
CA2307911A1 (en) * 1999-11-18 2001-05-18 Loran Network Management Ltd. Method for determining the delay and jitter in communication between objects in a connected network
US6460001B1 (en) * 2000-03-29 2002-10-01 Advantest Corporation Apparatus for and method of measuring a peak jitter
WO2003007578A1 (en) * 2001-07-13 2003-01-23 Anritsu Corporation Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation
US6651016B1 (en) * 2001-12-21 2003-11-18 Credence Systems Corporation Jitter-corrected spectrum analyzer
JP2004093345A (ja) * 2002-08-30 2004-03-25 Renesas Technology Corp ジッタ測定回路
US20040062301A1 (en) * 2002-09-30 2004-04-01 Takahiro Yamaguchi Jitter measurement apparatus and jitter measurement method
US6701269B1 (en) * 2003-01-28 2004-03-02 Agilent Technologies, Inc. Jitter measurement extrapolation and calibration for bit error ratio detection
JP2004310567A (ja) * 2003-04-09 2004-11-04 Matsushita Electric Ind Co Ltd クロックばらつきタイミング解析方法
JP2005004268A (ja) * 2003-06-09 2005-01-06 Matsushita Electric Ind Co Ltd 半導体集積回路装置の動作解析方法、これに用いられる解析装置およびこれを用いた最適化設計方法
US7158899B2 (en) * 2003-09-25 2007-01-02 Logicvision, Inc. Circuit and method for measuring jitter of high speed signals
JP2005122298A (ja) * 2003-10-14 2005-05-12 Fujitsu Ltd タイミング解析装置、タイミング解析方法及びプログラム
US7002358B2 (en) * 2003-12-10 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for measuring jitter
WO2005060655A2 (en) * 2003-12-16 2005-07-07 California Institute Of Technology Deterministic jitter equalizer
US7236555B2 (en) * 2004-01-23 2007-06-26 Sunrise Telecom Incorporated Method and apparatus for measuring jitter
US7203610B2 (en) * 2004-08-31 2007-04-10 Guide Technology, Inc. System and method of obtaining data-dependent jitter (DDJ) estimates from measured signal data
JP2006214987A (ja) * 2005-02-07 2006-08-17 Nec Electronics Corp ノイズ測定システムおよび方法ならびに半導体装置

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US7295938B2 (en) 2007-11-13
US20060220751A1 (en) 2006-10-05
JP2006277557A (ja) 2006-10-12

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