JP4451189B2 - 試験装置、位相調整方法、及びメモリコントローラ - Google Patents

試験装置、位相調整方法、及びメモリコントローラ Download PDF

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Publication number
JP4451189B2
JP4451189B2 JP2004111494A JP2004111494A JP4451189B2 JP 4451189 B2 JP4451189 B2 JP 4451189B2 JP 2004111494 A JP2004111494 A JP 2004111494A JP 2004111494 A JP2004111494 A JP 2004111494A JP 4451189 B2 JP4451189 B2 JP 4451189B2
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JP
Japan
Prior art keywords
signal
output
timing
memory
under test
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Expired - Fee Related
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JP2004111494A
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English (en)
Japanese (ja)
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JP2005293808A5 (enExample
JP2005293808A (ja
Inventor
新哉 佐藤
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Advantest Corp
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Advantest Corp
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Publication date
Priority to JP2004111494A priority Critical patent/JP4451189B2/ja
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to CNB2005800101694A priority patent/CN100505107C/zh
Priority to KR1020067023285A priority patent/KR100840800B1/ko
Priority to PCT/JP2005/005547 priority patent/WO2005098868A1/ja
Priority to DE112005000745T priority patent/DE112005000745T5/de
Priority to US11/180,895 priority patent/US7266738B2/en
Publication of JP2005293808A publication Critical patent/JP2005293808A/ja
Publication of JP2005293808A5 publication Critical patent/JP2005293808A5/ja
Application granted granted Critical
Publication of JP4451189B2 publication Critical patent/JP4451189B2/ja
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Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2004111494A 2004-04-05 2004-04-05 試験装置、位相調整方法、及びメモリコントローラ Expired - Fee Related JP4451189B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2004111494A JP4451189B2 (ja) 2004-04-05 2004-04-05 試験装置、位相調整方法、及びメモリコントローラ
KR1020067023285A KR100840800B1 (ko) 2004-04-05 2005-03-25 시험 장치, 위상 조정 방법, 및 메모리 제어기
PCT/JP2005/005547 WO2005098868A1 (ja) 2004-04-05 2005-03-25 試験装置、位相調整方法、及びメモリコントローラ
DE112005000745T DE112005000745T5 (de) 2004-04-05 2005-03-25 Testgerät, Phaseneinstellverfahren und Speichersteuerung
CNB2005800101694A CN100505107C (zh) 2004-04-05 2005-03-25 测试装置、相位调整方法及存储器控制器
US11/180,895 US7266738B2 (en) 2004-04-05 2005-07-13 Test apparatus, phase adjusting method and memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004111494A JP4451189B2 (ja) 2004-04-05 2004-04-05 試験装置、位相調整方法、及びメモリコントローラ

Publications (3)

Publication Number Publication Date
JP2005293808A JP2005293808A (ja) 2005-10-20
JP2005293808A5 JP2005293808A5 (enExample) 2008-08-21
JP4451189B2 true JP4451189B2 (ja) 2010-04-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004111494A Expired - Fee Related JP4451189B2 (ja) 2004-04-05 2004-04-05 試験装置、位相調整方法、及びメモリコントローラ

Country Status (6)

Country Link
US (1) US7266738B2 (enExample)
JP (1) JP4451189B2 (enExample)
KR (1) KR100840800B1 (enExample)
CN (1) CN100505107C (enExample)
DE (1) DE112005000745T5 (enExample)
WO (1) WO2005098868A1 (enExample)

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US7254763B2 (en) * 2004-09-01 2007-08-07 Agere Systems Inc. Built-in self test for memory arrays using error correction coding
KR100639678B1 (ko) * 2004-11-16 2006-10-30 삼성전자주식회사 테스트 장치
US7856578B2 (en) * 2005-09-23 2010-12-21 Teradyne, Inc. Strobe technique for test of digital signal timing
US7574632B2 (en) * 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for time stamping a digital signal
US7573957B2 (en) * 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for recovering a clock in a digital signal
JP4949707B2 (ja) * 2006-03-22 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置及びそのテスト方法
US7603246B2 (en) * 2006-03-31 2009-10-13 Nvidia Corporation Data interface calibration
US7715251B2 (en) * 2006-10-25 2010-05-11 Hewlett-Packard Development Company, L.P. Memory access strobe configuration system and process
US7797121B2 (en) * 2007-06-07 2010-09-14 Advantest Corporation Test apparatus, and device for calibration
JP4985177B2 (ja) * 2007-07-25 2012-07-25 富士通株式会社 高速製品の試験方法及び装置
WO2009025020A1 (ja) * 2007-08-20 2009-02-26 Advantest Corporation 試験装置、試験方法、および、製造方法
US8521979B2 (en) 2008-05-29 2013-08-27 Micron Technology, Inc. Memory systems and methods for controlling the timing of receiving read data
US7855931B2 (en) 2008-07-21 2010-12-21 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
US8756486B2 (en) 2008-07-02 2014-06-17 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
US8289760B2 (en) 2008-07-02 2012-10-16 Micron Technology, Inc. Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
JP5171442B2 (ja) * 2008-07-08 2013-03-27 株式会社アドバンテスト マルチストローブ回路および試験装置
US7808849B2 (en) * 2008-07-08 2010-10-05 Nvidia Corporation Read leveling of memory units designed to receive access requests in a sequential chained topology
US7796465B2 (en) * 2008-07-09 2010-09-14 Nvidia Corporation Write leveling of memory units designed to receive access requests in a sequential chained topology
US8461884B2 (en) * 2008-08-12 2013-06-11 Nvidia Corporation Programmable delay circuit providing for a wide span of delays
US7768255B2 (en) 2008-08-28 2010-08-03 Advantest Corporation Interconnection substrate, skew measurement method, and test apparatus
WO2010058441A1 (ja) * 2008-11-19 2010-05-27 株式会社アドバンテスト 試験装置、試験方法、および、プログラム
US8274272B2 (en) * 2009-02-06 2012-09-25 Advanced Micro Devices, Inc. Programmable delay module testing device and methods thereof
JP5311047B2 (ja) * 2009-09-11 2013-10-09 日本電気株式会社 半導体記憶装置の試験方法
JP5477062B2 (ja) * 2010-03-08 2014-04-23 富士通セミコンダクター株式会社 半導体集積回路の試験装置、試験方法、及びプログラム
US8400808B2 (en) 2010-12-16 2013-03-19 Micron Technology, Inc. Phase interpolators and push-pull buffers
US8612815B2 (en) * 2011-12-16 2013-12-17 International Business Machines Corporation Asynchronous circuit with an at-speed built-in self-test (BIST) architecture
US8972818B2 (en) * 2012-10-05 2015-03-03 Qualcomm Incorporated Algorithm for optimal usage of external memory tuning sequence
US9171597B2 (en) * 2013-08-30 2015-10-27 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories
CN104764914A (zh) * 2014-01-03 2015-07-08 致茂电子股份有限公司 误差补偿方法与应用此方法的自动测试设备
CN104616697A (zh) * 2014-12-17 2015-05-13 曙光信息产业(北京)有限公司 Qdr-sram的时钟相位调整方法和装置
TWI562541B (en) * 2015-12-09 2016-12-11 Chroma Ate Inc Wave form generating apparatus capable of calibration and calibrating method thereof
US10867642B2 (en) 2016-05-17 2020-12-15 Taiwan Semiconductor Manufacturing Company Limited Active random access memory
CN114062889B (zh) * 2020-08-04 2024-08-27 瑞昱半导体股份有限公司 检测电路运行速度的余量的装置
CN113868107B (zh) * 2021-09-10 2024-04-26 长沙市致存科技有限责任公司 存储产品后端io的自适应调整方法、装置、设备及介质
US11726904B2 (en) 2021-09-23 2023-08-15 International Business Machines Corporation Controlled input/output in progress state during testcase processing
CN114116581A (zh) * 2021-10-14 2022-03-01 北京国科天迅科技有限公司 提高高速串行总线突发传输响应性能的方法及装置
KR20240056205A (ko) * 2022-10-21 2024-04-30 매그나칩믹스드시그널 유한회사 메모리 리페어 장치

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JP3636506B2 (ja) * 1995-06-19 2005-04-06 株式会社アドバンテスト 半導体試験装置
JP3607325B2 (ja) * 1994-09-22 2005-01-05 株式会社アドバンテスト 半導体試験装置用比較回路
US5732047A (en) * 1995-12-12 1998-03-24 Advantest Corporation Timing comparator circuit for use in device testing apparatus
JPH09166646A (ja) * 1995-12-15 1997-06-24 Nec Corp 半導体装置
TW343282B (en) * 1996-06-14 1998-10-21 Adoban Tesuto Kk Testing device for a semiconductor device
JP3718374B2 (ja) * 1999-06-22 2005-11-24 株式会社東芝 メモリ混載半導体集積回路装置及びそのテスト方法
WO2001013136A1 (fr) * 1999-08-16 2001-02-22 Advantest Corporation Procede de correcteur de synchronisation pour testeur de circuit integre et testeur de circuit integre a fonctions correctrices utilisant ledit procede
JP2001222897A (ja) * 2000-02-04 2001-08-17 Advantest Corp 半導体試験装置
JP4291494B2 (ja) * 2000-04-04 2009-07-08 株式会社アドバンテスト Ｉｃ試験装置のタイミング校正装置
US6377065B1 (en) * 2000-04-13 2002-04-23 Advantest Corp. Glitch detection for semiconductor test system
JP2002181899A (ja) * 2000-12-15 2002-06-26 Advantest Corp タイミング校正方法
JP2003098235A (ja) * 2001-09-27 2003-04-03 Matsushita Electric Ind Co Ltd 半導体集積回路およびその検査方法

Also Published As

Publication number Publication date
US20060041799A1 (en) 2006-02-23
KR20070001264A (ko) 2007-01-03
KR100840800B1 (ko) 2008-06-23
DE112005000745T5 (de) 2007-02-22
CN100505107C (zh) 2009-06-24
JP2005293808A (ja) 2005-10-20
CN1938788A (zh) 2007-03-28
WO2005098868A1 (ja) 2005-10-20
US7266738B2 (en) 2007-09-04

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