JP4424830B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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JP4424830B2
JP4424830B2 JP2000198120A JP2000198120A JP4424830B2 JP 4424830 B2 JP4424830 B2 JP 4424830B2 JP 2000198120 A JP2000198120 A JP 2000198120A JP 2000198120 A JP2000198120 A JP 2000198120A JP 4424830 B2 JP4424830 B2 JP 4424830B2
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Prior art keywords
guard ring
metal film
semiconductor device
metal
diffusion region
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JP2002016227A (ja
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忠正 村上
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Priority to JP2000198120A priority Critical patent/JP4424830B2/ja
Priority to US09/717,308 priority patent/US6555884B1/en
Publication of JP2002016227A publication Critical patent/JP2002016227A/ja
Priority to US10/387,500 priority patent/US6787873B2/en
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置、特にその雑音遮蔽のためのガードリングの構造に関するものである。
【０００２】
【従来の技術】
従来、半導体装置では、半導体基板上に形成されたトランジスタの周囲をガードリングと呼ばれる導電性の領域で取り囲み、このガードリングを接地電位に接続してトランジスタに入力する外部雑音を遮蔽することが行われている。
【０００３】
【発明が解決しようとする課題】
しかしながら、従来の半導体装置では、次のような課題があった。
ガードリングは、半導体基板上のトランジスタ形成領域の周囲にイオンを高濃度に拡散して導電性を持たせた領域として形成される。このため、ガードリングの抵抗分を完全に０にすることが困難であり、特に増幅度の高いトランジスタの場合、外部雑音の影響を完全に遮蔽することができなかった。
本発明は、前記従来技術が持っていた課題を解決し、外部雑音を効果的に遮蔽することができるガードリングを備えた半導体装置を提供するものである。
【０００４】
【課題を解決するための手段】
【０００６】
前記課題を解決するために、本発明は、半導体装置において、第１導電型の半導体基板上に形成されたトランジスタを含む回路領域と、前記回路領域の周囲を取り囲んで形成された高濃度の第１導電型のイオン拡散領域による第１のガードリングと、前記第１のガードリングの周囲を取り囲むように第２導電型のイオンを高濃度に拡散した拡散領域と、前記拡散領域の周囲を取り囲んで形成された第１導電型のイオン拡散領域による第２のガードリングと、絶縁膜を介して前記第１のガードリングに対向して形成されて該第１のガードリングとの間が複数の層間配線で接続された第１の金属膜パターンと、前記絶縁膜を介して前記第２のガードリングに対向して形成されて該第２のガードリングとの間が複数の層間配線で接続された第２の金属膜パターンと、前記絶縁膜を介して前記拡散領域に対向して形成されて該拡散領域との間が複数の層間配線で接続された第３の金属膜パターンと、前記第１の金属膜パターンを基準電位が与えられる外部端子に接続する第１の金属線と、前記第２の金属膜パターンを前記外部端子に接続する第２の金属線と、前記第３の金属膜パターンを前記外部端子に接続する第３の金属線とを備えている。
【０００７】
本発明によれば、次のような作用が行われる。
第１導電型の第１及び第２のガードリングの間に形成された第２導電型の拡散領域により、ガードリング間に逆接続されたダイオードが形成される。該１及び第２のガードリングはそれぞれ個別に基準電位に接続されているので、逆接続されたダイオードにより、第２のガードリングから第１のガードリングを越えて回路領域に到達する外部雑音はほぼ完全になくなる。
【０００８】
【発明の実施の形態】
（第１の実施形態）
図１（ａ），（ｂ）は、本発明の第１の実施形態を示す半導体装置の構成図であり、同図（ａ）は平面図、及び同図（ｂ）は同図（ａ）中のＸ−Ｘ線による拡大断面図である。
図１（ａ）に示すように、この半導体装置は、集積回路（以下、「ＩＣ」という）チップ１０と、このＩＣチップ１０を搭載するパッケージ２０を備えている。ＩＣチップ１０は、例えばＰ型の半導体基板１１上にトランジスタを含む回路が形成されたトランジスタ形成領域１２を有している。トランジスタ形成領域１２の周囲には、第１のガードリング１３ａ形成され、更にこの第１のガードリング１３ａの周囲を囲むように第２のガードリング１３ｂが形成されている。
更に、ＩＣチップ１０の表面には、トランジスタ等の回路を外部へ接続するための複数の電極１４が形成されている。
【０００９】
パッケージ２０は、ＩＣチップ１０を機械的に固定して外部回路に接続するもので、絶縁性のパッケージ基板２１と、このパッケージ基板２１の周辺部に設けられた複数の金属製の外部端子２２を有している。更に、パッケージ２０の外部端子２２とＩＣチップ１０の電極１４の間は、金等の金属線２３を介して電気的に接続されている。
【００１０】
図１（ｂ）は、特にＩＣチップ１０におけるガードリングの構造を明らかにするための断面図であり、本発明に直接関係しないトランジスタ等の構造は省略している。
ＩＣチップ１０は、前述したように、Ｐ型の半導体基板１１上にトランジスタ形成領域１２が形成され、このトランジスタ形成領域１２の周囲を取り囲むように高濃度のＰ型イオンを拡散したガードリング１３ａが形成されている。更に、ガードリング１３ａの外側に、一定の間隔をあけてガードリング１３ｂが形成されている。このガードリング１３ｂも、ガードリング１３ａと同様に高濃度のＰ型イオンを拡散したものである。ガードリング１３ａ，１３ｂは、トランジスタ形成領域１２に形成されるトランジスタのソース・ドレイン領域よりも高い不純物濃度となっている。
【００１１】
トランジスタ形成領域１２、及びガードリング１３ａ，１３ｂが形成された半導体基板１１の表面には、酸化シリコン等の絶縁膜１５が形成されている。絶縁膜１５の表面で、ガードリング１３ａに対応する箇所には、金属膜１６ａが形成され、この金属膜１６ａとガードリング１３ａとの間が金属による複数の層間配線１７ａによって電気的に接続されている。
【００１２】
更に、絶縁膜１５の表面で、ガードリング１３ｂに対応する箇所には、金属膜１６ｂが形成され、この金属膜１６ｂとガードリング１３ｂとの間が金属による複数の層間配線１７ｂによって電気的に接続されている。金属膜１６ａ，１６ｂは、絶縁膜１５上に互いに電気的に独立して形成された電極１４ａ，１４ｂに、それぞれ接続されている。
このようなＩＣチップ１０は、パッケージ基板２１上に接着剤等で固定され、このＩＣチップ１０の電極１４ａ，１４ｂは、それぞれ個別の金属線２３ａ，２３ｂを介して、パッケージ２０に共通の基準電位を与えるための外部電極２２に接続されている。
【００１３】
図２は、図１中のガードリングの等価回路図である。以下、この図２を参照しつつ、図１におけるガードリングの動作及び効果を説明する。
ガードリング１３ａは、複数の層間配線１７ａによって金属膜１６ａに電気的に接続されているので、このガードリング１３ａ及び金属膜１６ａの電位は、その位置に関係なく常にほぼ同一電位となる。同様に、ガードリング１３ｂは、複数の層間配線１７ｂによって金属膜１６ｂに電気的に接続されているので、このガードリング１３ｂ及び金属膜１６ｂの電位は、その位置に関係なく常にほぼ同一電位となる。
【００１４】
図２において、ノードＡは、例えば外部からの雑音電圧Ｖｎが与えられるＩＣチップ１０の電極１４ｎに対応する。ノードＰａ，Ｐｂは、それぞれガードリング１３ａ，１３ｂに対応する。また、ノードＣＯＭは、パッケージ２０における基準電位の電極２２に対応している。更に、ノードＢは、ＩＣチップ１０上のトランジスタ形成領域１２中のトランジスタのゲート等の入力端子に対応している。
【００１５】
図２に示すように、ノードＡとノードＰｂの間は、半導体基板１１の基板抵抗Ｒ１で接続される。ノードＰｂは、金属線２３ｂのインピーダンスＺｂでノードＣＯＭに接続されると共に、半導体基板１１の基板抵抗Ｒ２でノードＰａに接続される。基板抵抗Ｒ２は、ガードリング１３ｂ，１３ａを最短距離で結ぶ基板抵抗Ｒ２ａと、半導体基板１１の内部を通して接続する基板抵抗Ｒ２ｂの合成抵抗となっている。
【００１６】
更に、ノードＰａは、金属線２３ａのインピーダンスＺａでノードＣＯＭに接続されると共に、基板抵抗Ｒ３を介してノードＢに接続される。ここで、ノードＢに接続されるトランジスタ等の入力インピーダンスを無限大とすれば、このノードＢの雑音電圧Ｖｂと、外部からの雑音電圧Ｖｎの比は、次の（１）式のようになる。
【数１】
Figure 0004424830
【００１７】
ここで、金属線２３ａ，２３ｂのインピーダンスＺａ，Ｚｂは、抵抗Ｒ１，Ｒ２に比べて極めて小さいので、（１）式は、次の（２）式で近似される。
Ｖｂ／Ｖｎ＝Ｚｂ・Ｚａ／（Ｒ１＋Ｚｂ）・（Ｒ２＋Ｚａ） ・・・（２）
従って、ノードＢの雑音電圧Ｖｂは、入力された雑音電圧Ｖｎより減衰されて極めて小さな値となる。
以上のように、この第１の実施形態の半導体装置は、それぞれ独立して基準電位に接続された２重のガードリング１３ａ，１３ｂを有するため、外部雑音を効果的に遮蔽することができる。
【００１８】
（第２の実施形態）
図３（ａ），（ｂ）は、本発明の第２の実施形態を示す半導体装置の構成図と等価回路図である。図３（ａ）は、図１（ｂ）に対応してガードリングの構造を明らかにするための断面図である。図３（ａ），（ｂ）において、図１及び図２中の要素と共通の要素には共通の符号が付されている。
この図３（ａ）の半導体装置では、図１の半導体装置におけるガードリング１３ａ，１３ｂ間に、これらを分離するための溝を設け、この溝の内部に酸化シリコン等の絶縁物１８を充填している。その他の構成は、図１と同様である。
【００１９】
図３（ｂ）に示すように、この半導体装置のガードリングの等価回路は、図２中の基板抵抗Ｒ２が基板インピーダンスＺ２で置換されたものになる。基板インピーダンスＺ２は、ガードリング１３ａ，１３ｂ間の絶縁物１８によるキャパシタンスＣ２と、半導体基板１１の内部を通して接続する基板抵抗Ｒ２ｂの合成インピーダンスとなっている。即ち、図３（ｂ）中の基板インピーダンスＺ２は、図２中の基板抵抗Ｒ２よりも大きな値となる。従って、前記（２）式から明らかなように、第１の実施形態に比べて、ノードＢの雑音電圧Ｖｂが更に減衰されることが分かる。
以上のように、この第２の実施形態の半導体装置は、それぞれ独立して基準電位に接続された２重のガードリング１３ａ，１３ｂの間に、絶縁物１８を設けている。これにより、更に効果的に外部雑音を遮蔽することができる。
【００２０】
（第３の実施形態）
図４（ａ），（ｂ）は、本発明の第３の実施形態を示す半導体装置の構成図と等価回路図である。図４（ａ）は、図１（ｂ）に対応してガードリングの構造を明らかにするための断面図である。図４（ａ），（ｂ）において、図１及び図２中の要素と共通の要素には共通の符号が付されている。
この図４（ａ）の半導体装置では、図１の半導体装置におけるガードリング１３ａ，１３ｂ間に、高濃度のＮ型イオンを拡散したＮ型領域１９を設けている。また、絶縁膜１５の表面でＮ型領域１９に対応する箇所には、金属膜１６ｃが形成され、この金属膜１６ｃとＮ型領域１９との間が金属による複数の層間配線１７ｃで電気的に接続されている。金属膜１６ｃは、絶縁膜１５上に形成された電極１４ｃに接続され、この電極１４ｃは金属線２３ｃを介して、パッケージ２０に基準電位を与えるための外部電極２２に接続されている。その他の構成は、図１と同様である。
【００２１】
図４（ｂ）に示すように、この半導体装置のガードリングの等価回路は、図２中の基板抵抗Ｒ２が半導体回路ＣＴ２で置換されたものになる。半導体回路ＣＴ２は、ガードリング１３ａとＮ型領域１９で形成されるダイオードＤａ、このＮ型領域１９とガードリング１３ｂで形成されるダイオードＤｂ、半導体基板１１の内部を通して接続する基板抵抗Ｒ２ｂ、及びダイオードＤａ，Ｄｂの陽極（即ち、金属膜１６ｃ）と外部電極２２を接続する金属線２３ｃのインピーダンスＺｃで構成されている。
これにより、等価的にガードリングが３重に構成されたものとなり、更に一層の遮蔽効果を得ることができる。
以上のように、この第３の実施形態の半導体装置は、それぞれ独立して基準電位に接続された２重のガードリング１３ａ，１３ｂの間に、Ｎ型領域１９を設け、このＮ型領域１９を独立して基準電位に接続している。これにより、第２の実施形態に比べて更に効果的に外部雑音を遮蔽することができる。
【００２２】
なお、本発明は、上記実施形態に限定されず、種々の変形が可能である。この変形例としては、例えば、次の（ａ）〜（ｃ）のようなものがある。
（ａ） Ｐ型の半導体基板を用いているが、Ｎ型の半導体基板でも同様に適用可能である。
（ｂ） ガードリングを２重にした構成としているが、２重以上であれば何重でも良い。
（ｃ） 図４の半導体装置では、Ｎ型領域１９を基準電位に接続するように構成しているが、図３と同様に単にＮ型領域１９を設けるだけでも良い。この場合、図４に比べて遮蔽効果が若干減少するが、構造が簡素化できる。
【００２３】
【発明の効果】
【００２４】
本発明によれば、ガードリングを２重に設け、これらのガードリングを第１及び第２の金属膜パターンに接続してガードリング上の電位差を無くすと共に、この第１及び第２の金属膜パターンを個別に基準電位に接続し、更に、第１及び第２のガードリングの間に、逆接続のダイオードを構成するための拡散領域を設けている。これにより、大きな遮蔽効果を得ることができる。しかも、拡散領域を基準電位に接続している。これにより、等価的に３重のガードリング構成となり、更に大きな遮蔽効果を得ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示す半導体装置の構成図である。
【図２】図１中のガードリングの等価回路図である。
【図３】本発明の第２の実施形態を示す半導体装置の構成図と等価回路図である。
【図４】本発明の第３の実施形態を示す半導体装置の構成図と等価回路図である。
【符号の説明】
１０ ＩＣチップ
１１ 半導体基板
１２ トランジスタ形成領域
１３ａ，１３ｂ ガードリング
１４ａ，１４ｂ，１４ｃ，１４ｎ 電極
１５ 絶縁膜
１６ａ，１６ｂ，１６ｃ 金属膜
１７ａ，１７ｂ，１７ｃ 層間配線
１８ 絶縁物
１９ Ｎ型領域
２０ パッケージ
２１ パッケージ基板
２２ 外部端子
２３ａ，２３ｂ，２３ｃ 金属線

Claims (1)

  1. 第１導電型の半導体基板上に形成されたトランジスタを含む回路領域と、
    前記回路領域の周囲を取り囲んで形成された高濃度の第１導電型のイオン拡散領域による第１のガードリングと、
    前記第１のガードリングの周囲を取り囲むように第２導電型のイオンを高濃度に拡散した拡散領域と、
    前記拡散領域の周囲を取り囲んで形成された第１導電型のイオン拡散領域による第２のガードリングと、
    絶縁膜を介して前記第１のガードリングに対向して形成されて該第１のガードリングとの間が複数の層間配線で接続された第１の金属膜パターンと、
    前記絶縁膜を介して前記第２のガードリングに対向して形成されて該第２のガードリングとの間が複数の層間配線で接続された第２の金属膜パターンと、
    前記絶縁膜を介して前記拡散領域に対向して形成されて該拡散領域との間が複数の層間配線で接続された第３の金属膜パターンと、
    前記第１の金属膜パターンを基準電位が与えられる外部端子に接続する第１の金属線と、
    前記第２の金属膜パターンを前記外部端子に接続する第２の金属線と、
    前記第３の金属膜パターンを前記外部端子に接続する第３の金属線と、
    を備えたことを特徴とする半導体装置。
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