JP4615229B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4615229B2 JP4615229B2 JP2004054408A JP2004054408A JP4615229B2 JP 4615229 B2 JP4615229 B2 JP 4615229B2 JP 2004054408 A JP2004054408 A JP 2004054408A JP 2004054408 A JP2004054408 A JP 2004054408A JP 4615229 B2 JP4615229 B2 JP 4615229B2
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- 239000004065 semiconductor Substances 0.000 title claims description 69
- 239000000758 substrate Substances 0.000 claims description 92
- 238000009792 diffusion process Methods 0.000 claims description 38
- 230000005669 field effect Effects 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001902 propagating effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 229910052710 silicon Inorganic materials 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 238000000034 method Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000000644 propagated effect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
2、3、102、103;回路領域
2a、3a、102a、103a、104;p+拡散領域
5、105;STI領域
6、106;Pウエル
7、107;基板ノイズ
8;絶縁膜
9;電極
10;空乏層
Claims (9)
- 第1導電型の半導体基板と、
該半導体基板の表面に形成され、それぞれに第1導電型の拡散領域が形成された、複数の回路領域と、
前記半導体基板上における前記複数の回路領域間の領域に設けられた絶縁膜と、
該絶縁膜上に設けられた電極と、
前記半導体基板の表面における前記複数の回路領域間であって、前記電極の直下域を除く領域に形成されたSTI領域と、を有し、
前記半導体基板の表面における前記電極の直下域は、不純物が注入されていないノンドープ領域であり、
前記電極には、前記半導体基板の表面における該電極の直下域に空乏層を形成して前記回路領域間を伝搬する基板ノイズを阻止するような電位が印加され、
該空乏層がガードリングとして機能することを特徴とする半導体装置。 - 前記拡散領域の不純物濃度は、前記半導体基板の不純物濃度よりも高く、
該拡散領域は、前記電極と離れて形成されている、ことを特徴とする請求項1に記載の半導体装置。 - 前記半導体基板がP型の半導体基板であり、前記電位が正極の電源電位であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記半導体基板がN型の半導体基板であり、前記電位が負極の電源電位であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記回路領域に電界効果トランジスタが形成されており、前記絶縁膜が該電界効果トランジスタのゲート絶縁膜と同時に形成されたものであり、前記電極が前記電界効果トランジスタのゲート電極と同時に形成されたものであることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
- 前記電極及び前記絶縁膜が1つの前記回路領域を囲むように形成されていることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
- 前記半導体基板の表面領域のうち、前記拡散領域と前記電極の直下域とを除く領域の一部に形成された第1導電型のウェルをさらに備え、
前記STI領域は、該ウェル上に形成されており、
前記拡散領域は、前記ウェルよりも深く形成されていることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。 - 前記電極の直下域の前記半導体基板の表面は、前記STI領域の表面と同じ高さであり、
前記絶縁膜は、該電極の直下域の半導体基板上に形成されていることを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置。 - 前記空乏層は、前記拡散領域よりも深いことを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054408A JP4615229B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置 |
US11/066,534 US7339249B2 (en) | 2004-02-27 | 2005-02-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054408A JP4615229B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005244077A JP2005244077A (ja) | 2005-09-08 |
JP4615229B2 true JP4615229B2 (ja) | 2011-01-19 |
Family
ID=34879744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004054408A Expired - Fee Related JP4615229B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7339249B2 (ja) |
JP (1) | JP4615229B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4644006B2 (ja) * | 2005-03-02 | 2011-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8587023B2 (en) * | 2005-05-25 | 2013-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Guard rings with local coupling capacitance |
US7863714B2 (en) * | 2006-06-05 | 2011-01-04 | Akustica, Inc. | Monolithic MEMS and integrated circuit device having a barrier and method of fabricating the same |
JP5090696B2 (ja) * | 2006-09-12 | 2012-12-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8492873B1 (en) | 2010-03-04 | 2013-07-23 | Altera Corporation | Integrated circuit guard ring structures |
US8097925B2 (en) * | 2010-03-26 | 2012-01-17 | Altera Corporation | Integrated circuit guard rings |
US8866527B1 (en) | 2010-04-02 | 2014-10-21 | Altera Corporation | Integrated circuits with hold time avoidance circuitry |
KR101414005B1 (ko) * | 2013-10-31 | 2014-07-04 | 주식회사 케이이씨 | 과도 전압 억제 소자 및 그 제조 방법 |
US20150228714A1 (en) * | 2014-02-13 | 2015-08-13 | Rfaxis, Inc. | Isolation methods for leakage, loss and non-linearity mitigation in radio-frequency integrated circuits on high-resistivity silicon-on-insulator substrates |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6394667A (ja) * | 1986-10-08 | 1988-04-25 | Fuji Electric Co Ltd | 半導体集積回路 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4990974A (en) * | 1989-03-02 | 1991-02-05 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor |
US5369295A (en) * | 1992-01-28 | 1994-11-29 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor with reduced gate and diffusion capacitance |
US5973382A (en) * | 1993-07-12 | 1999-10-26 | Peregrine Semiconductor Corporation | Capacitor on ultrathin semiconductor on insulator |
JP2000049286A (ja) | 1996-01-29 | 2000-02-18 | Toshiba Microelectronics Corp | 半導体装置 |
US5952701A (en) * | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
JP2001345428A (ja) * | 2000-03-27 | 2001-12-14 | Toshiba Corp | 半導体装置とその製造方法 |
JP4424830B2 (ja) | 2000-06-30 | 2010-03-03 | Okiセミコンダクタ株式会社 | 半導体装置 |
US20030134479A1 (en) * | 2002-01-16 | 2003-07-17 | Salling Craig T. | Eliminating substrate noise by an electrically isolated high-voltage I/O transistor |
TW536802B (en) * | 2002-04-22 | 2003-06-11 | United Microelectronics Corp | Structure and fabrication method of electrostatic discharge protection circuit |
US7180158B2 (en) * | 2005-06-02 | 2007-02-20 | Freescale Semiconductor, Inc. | Semiconductor device and method of manufacture |
-
2004
- 2004-02-27 JP JP2004054408A patent/JP4615229B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-28 US US11/066,534 patent/US7339249B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6394667A (ja) * | 1986-10-08 | 1988-04-25 | Fuji Electric Co Ltd | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
JP2005244077A (ja) | 2005-09-08 |
US20050189602A1 (en) | 2005-09-01 |
US7339249B2 (en) | 2008-03-04 |
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