JP4401621B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP4401621B2
JP4401621B2 JP2002131100A JP2002131100A JP4401621B2 JP 4401621 B2 JP4401621 B2 JP 4401621B2 JP 2002131100 A JP2002131100 A JP 2002131100A JP 2002131100 A JP2002131100 A JP 2002131100A JP 4401621 B2 JP4401621 B2 JP 4401621B2
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JP
Japan
Prior art keywords
circuit
substrate bias
bias
substrate
switch control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002131100A
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English (en)
Japanese (ja)
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JP2003324158A (ja
JP2003324158A5 (enExample
Inventor
祐行 宮崎
雄介 菅野
豪一 小野
利信 新保
義彦 安
一正 柳沢
孝 倉石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2002131100A priority Critical patent/JP4401621B2/ja
Priority to US10/429,771 priority patent/US7612604B2/en
Publication of JP2003324158A publication Critical patent/JP2003324158A/ja
Publication of JP2003324158A5 publication Critical patent/JP2003324158A5/ja
Application granted granted Critical
Publication of JP4401621B2 publication Critical patent/JP4401621B2/ja
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2002131100A 2002-05-07 2002-05-07 半導体集積回路装置 Expired - Fee Related JP4401621B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002131100A JP4401621B2 (ja) 2002-05-07 2002-05-07 半導体集積回路装置
US10/429,771 US7612604B2 (en) 2002-05-07 2003-05-06 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002131100A JP4401621B2 (ja) 2002-05-07 2002-05-07 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2003324158A JP2003324158A (ja) 2003-11-14
JP2003324158A5 JP2003324158A5 (enExample) 2005-09-22
JP4401621B2 true JP4401621B2 (ja) 2010-01-20

Family

ID=29543870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002131100A Expired - Fee Related JP4401621B2 (ja) 2002-05-07 2002-05-07 半導体集積回路装置

Country Status (2)

Country Link
US (1) US7612604B2 (enExample)
JP (1) JP4401621B2 (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
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US7205758B1 (en) 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US6897671B1 (en) * 2004-03-01 2005-05-24 Transmeta Corporation System and method for reducing heat dissipation during burn-in
US6900650B1 (en) * 2004-03-01 2005-05-31 Transmeta Corporation System and method for controlling temperature during burn-in
US7248988B2 (en) * 2004-03-01 2007-07-24 Transmeta Corporation System and method for reducing temperature variation during burn in
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7129745B2 (en) * 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
WO2005125012A1 (en) * 2004-06-15 2005-12-29 Koninklijke Philips Electronics N.V. Adaptive control of power supply for integrated circuits
US7509504B1 (en) * 2004-09-30 2009-03-24 Transmeta Corporation Systems and methods for control of integrated circuits comprising body biasing systems
JP4835856B2 (ja) * 2005-01-06 2011-12-14 日本電気株式会社 半導体集積回路装置
JP2007103863A (ja) * 2005-10-07 2007-04-19 Nec Electronics Corp 半導体デバイス
JP5105462B2 (ja) * 2005-12-27 2012-12-26 ルネサスエレクトロニクス株式会社 半導体集積回路
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7495471B2 (en) 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7330049B2 (en) 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US7902611B1 (en) * 2007-11-27 2011-03-08 Altera Corporation Integrated circuit well isolation structures
US7952423B2 (en) * 2008-09-30 2011-05-31 Altera Corporation Process/design methodology to enable high performance logic and analog circuits using a single process
JP4972634B2 (ja) * 2008-12-17 2012-07-11 株式会社日立製作所 半導体装置
CN102396156A (zh) * 2009-02-12 2012-03-28 莫塞德技术公司 用于片内终结的终结电路
US7969186B2 (en) * 2009-06-02 2011-06-28 Mips Technologies Apparatus and method for forming a mixed signal circuit with fully customizable analog cells and programmable interconnect
US8228115B1 (en) * 2009-06-22 2012-07-24 Xilinx, Inc. Circuit for biasing a well from three voltages
JP5466485B2 (ja) * 2009-11-12 2014-04-09 ルネサスエレクトロニクス株式会社 マイクロコンピュータ
JP2011166153A (ja) * 2010-02-12 2011-08-25 Samsung Electronics Co Ltd ガードリング構造を有する半導体デバイス、ディスプレイドライバ回路、及びディスプレイ装置
US8536674B2 (en) * 2010-12-20 2013-09-17 General Electric Company Integrated circuit and method of fabricating same
US9013228B2 (en) * 2011-06-20 2015-04-21 Stmicroelectronics Sa Method for providing a system on chip with power and body bias voltages
FR2976723A1 (fr) * 2011-06-20 2012-12-21 St Microelectronics Sa Procede d'alimentation et de polarisation de caissons d'un systeme integre sur puce
US8723592B2 (en) * 2011-08-12 2014-05-13 Nxp B.V. Adjustable body bias circuit
JP5946318B2 (ja) * 2012-05-02 2016-07-06 株式会社半導体エネルギー研究所 半導体装置
US8963627B2 (en) 2013-06-05 2015-02-24 Via Technologies, Inc. Digital power gating with controlled resume
US9000834B2 (en) * 2013-06-05 2015-04-07 Via Technologies, Inc. Digital power gating with global voltage shift
US9450580B2 (en) 2013-06-05 2016-09-20 Via Technologies, Inc. Digital power gating with programmable control parameter
US9007122B2 (en) 2013-06-05 2015-04-14 Via Technologies, Inc. Digital power gating with state retention
JP6384210B2 (ja) * 2014-09-02 2018-09-05 株式会社ソシオネクスト 半導体装置
US9659933B2 (en) * 2015-04-27 2017-05-23 Stmicroelectronics International N.V. Body bias multiplexer for stress-free transmission of positive and negative supplies
FR3058564B1 (fr) * 2016-11-07 2019-05-31 Stmicroelectronics Sa Procede et circuit de polarisation de circuits integres
US10101382B2 (en) * 2016-12-30 2018-10-16 Texas Instruments Incorporated Systems and methods for dynamic Rdson measurement
JP6538902B2 (ja) * 2018-02-14 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
US11262780B1 (en) * 2020-11-12 2022-03-01 Micron Technology, Inc. Back-bias optimization

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111343A (ja) 1982-12-16 1984-06-27 Nec Corp 集積回路装置
DE69328743T2 (de) 1992-03-30 2000-09-07 Mitsubishi Denki K.K., Tokio/Tokyo Halbleiteranordnung
JP2939086B2 (ja) 1992-03-30 1999-08-25 三菱電機株式会社 半導体装置
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
JP3814385B2 (ja) * 1997-10-14 2006-08-30 株式会社ルネサステクノロジ 半導体集積回路装置
JPH11135720A (ja) 1997-10-30 1999-05-21 Nec Corp 半導体集積回路
JP4109340B2 (ja) * 1997-12-26 2008-07-02 株式会社ルネサステクノロジ 半導体集積回路装置
JP4105833B2 (ja) 1998-09-09 2008-06-25 株式会社ルネサステクノロジ 半導体集積回路装置
TW453032B (en) 1998-09-09 2001-09-01 Hitachi Ltd Semiconductor integrated circuit apparatus
WO2002029893A1 (fr) 2000-10-03 2002-04-11 Hitachi, Ltd Dispositif à semi-conducteur
US6414534B1 (en) * 2001-02-20 2002-07-02 Taiwan Semiconductor Manufacturing Company Level shifter for ultra-deep submicron CMOS designs

Also Published As

Publication number Publication date
US20040016977A1 (en) 2004-01-29
JP2003324158A (ja) 2003-11-14
US7612604B2 (en) 2009-11-03

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