JP4343286B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4343286B2
JP4343286B2 JP19517198A JP19517198A JP4343286B2 JP 4343286 B2 JP4343286 B2 JP 4343286B2 JP 19517198 A JP19517198 A JP 19517198A JP 19517198 A JP19517198 A JP 19517198A JP 4343286 B2 JP4343286 B2 JP 4343286B2
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Japan
Prior art keywords
wafer
tape
flux
solder
grinding
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Expired - Lifetime
Application number
JP19517198A
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English (en)
Japanese (ja)
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JP2000031185A5 (enExample
JP2000031185A (ja
Inventor
勝 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP19517198A priority Critical patent/JP4343286B2/ja
Priority to TW088111432A priority patent/TW429398B/zh
Priority to KR1019990027176A priority patent/KR100572525B1/ko
Priority to US09/350,287 priority patent/US6060373A/en
Publication of JP2000031185A publication Critical patent/JP2000031185A/ja
Publication of JP2000031185A5 publication Critical patent/JP2000031185A5/ja
Application granted granted Critical
Publication of JP4343286B2 publication Critical patent/JP4343286B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)
JP19517198A 1998-07-10 1998-07-10 半導体装置の製造方法 Expired - Lifetime JP4343286B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP19517198A JP4343286B2 (ja) 1998-07-10 1998-07-10 半導体装置の製造方法
TW088111432A TW429398B (en) 1998-07-10 1999-07-06 Method for manufacturing a flip chip semiconductor device
KR1019990027176A KR100572525B1 (ko) 1998-07-10 1999-07-07 플립 칩 반도체 장치를 제조하는 방법
US09/350,287 US6060373A (en) 1998-07-10 1999-07-09 Method for manufacturing a flip chip semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19517198A JP4343286B2 (ja) 1998-07-10 1998-07-10 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2000031185A JP2000031185A (ja) 2000-01-28
JP2000031185A5 JP2000031185A5 (enExample) 2005-10-27
JP4343286B2 true JP4343286B2 (ja) 2009-10-14

Family

ID=16336632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19517198A Expired - Lifetime JP4343286B2 (ja) 1998-07-10 1998-07-10 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US6060373A (enExample)
JP (1) JP4343286B2 (enExample)
KR (1) KR100572525B1 (enExample)
TW (1) TW429398B (enExample)

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US6437591B1 (en) 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
JP3423245B2 (ja) 1999-04-09 2003-07-07 沖電気工業株式会社 半導体装置及びその実装方法
US6258703B1 (en) * 1999-07-21 2001-07-10 International Business Machines Corporation Reflow of low melt solder tip C4's
US6352881B1 (en) 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
JP2001094005A (ja) * 1999-09-22 2001-04-06 Oki Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
KR100674501B1 (ko) * 1999-12-24 2007-01-25 삼성전자주식회사 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법
US6656765B1 (en) * 2000-02-02 2003-12-02 Amkor Technology, Inc. Fabricating very thin chip size semiconductor packages
US6190943B1 (en) * 2000-06-08 2001-02-20 United Test Center Inc. Chip scale packaging method
TW452873B (en) * 2000-06-21 2001-09-01 Advanced Semiconductor Eng Manufacturing method of wafer scale semiconductor package structure
JP3485525B2 (ja) * 2000-07-06 2004-01-13 沖電気工業株式会社 半導体装置の製造方法
KR100394377B1 (ko) * 2000-09-07 2003-08-14 이진구 플립칩용 범프 제조 방법
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
US7174627B2 (en) * 2001-01-26 2007-02-13 Irvine Sensors Corporation Method of fabricating known good dies from packaged integrated circuits
US20030221313A1 (en) * 2001-01-26 2003-12-04 Gann Keith D. Method for making stacked integrated circuits (ICs) using prepackaged parts
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JP3530158B2 (ja) * 2001-08-21 2004-05-24 沖電気工業株式会社 半導体装置及びその製造方法
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US6638837B1 (en) * 2002-09-20 2003-10-28 Taiwan Semiconductor Manufacturing Company Method for protecting the front side of semiconductor wafers
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
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US7301222B1 (en) 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
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JP4049035B2 (ja) * 2003-06-27 2008-02-20 株式会社デンソー 半導体装置の製造方法
JP4260617B2 (ja) * 2003-12-24 2009-04-30 株式会社ルネサステクノロジ 半導体装置の製造方法
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JP4547187B2 (ja) * 2004-05-24 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100618543B1 (ko) * 2004-06-15 2006-08-31 삼성전자주식회사 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법
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JP2007123362A (ja) * 2005-10-25 2007-05-17 Disco Abrasive Syst Ltd デバイスの製造方法
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US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US9064716B2 (en) * 2009-09-30 2015-06-23 Virtium Technology, Inc. Stacking devices at finished package level
US9136144B2 (en) * 2009-11-13 2015-09-15 Stats Chippac, Ltd. Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
US8642390B2 (en) 2010-03-17 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Tape residue-free bump area after wafer back grinding
JP2012079910A (ja) * 2010-10-01 2012-04-19 Disco Abrasive Syst Ltd 板状物の加工方法
JP2012079911A (ja) * 2010-10-01 2012-04-19 Disco Abrasive Syst Ltd 板状物の加工方法
CN105097481A (zh) * 2014-04-24 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件的封装方法
JP7470411B2 (ja) * 2020-09-30 2024-04-18 フジコピアン株式会社 ウェーハ加工用積層体、それを用いた薄型ウェーハの製造方法及び薄型ウェーハ個片化の製造方法

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US5989939A (en) * 1996-12-13 1999-11-23 Tessera, Inc. Process of manufacturing compliant wirebond packages
US5909634A (en) * 1996-12-20 1999-06-01 Texas Instruments Method and apparatus for forming solder on a substrate
US5953623A (en) * 1997-04-10 1999-09-14 International Business Machines Corporation Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection

Also Published As

Publication number Publication date
US6060373A (en) 2000-05-09
KR20000011527A (ko) 2000-02-25
TW429398B (en) 2001-04-11
JP2000031185A (ja) 2000-01-28
KR100572525B1 (ko) 2006-04-24

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