JP4311376B2 - 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 - Google Patents

半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 Download PDF

Info

Publication number
JP4311376B2
JP4311376B2 JP2005168373A JP2005168373A JP4311376B2 JP 4311376 B2 JP4311376 B2 JP 4311376B2 JP 2005168373 A JP2005168373 A JP 2005168373A JP 2005168373 A JP2005168373 A JP 2005168373A JP 4311376 B2 JP4311376 B2 JP 4311376B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor substrate
electrically connected
semiconductor device
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005168373A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006344737A (ja
Inventor
春樹 伊東
伸晃 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2005168373A priority Critical patent/JP4311376B2/ja
Priority to US11/433,901 priority patent/US7495331B2/en
Priority to KR1020060045642A priority patent/KR20060128640A/ko
Priority to TW095119256A priority patent/TWI325686B/zh
Priority to EP06011084A priority patent/EP1732215B1/de
Priority to CNA2006100887627A priority patent/CN1877989A/zh
Publication of JP2006344737A publication Critical patent/JP2006344737A/ja
Priority to US12/237,750 priority patent/US8012864B2/en
Application granted granted Critical
Publication of JP4311376B2 publication Critical patent/JP4311376B2/ja
Priority to US12/947,861 priority patent/US8004077B2/en
Priority to US13/185,039 priority patent/US8294260B2/en
Priority to US13/624,324 priority patent/US8673767B2/en
Priority to US14/156,806 priority patent/US8896104B2/en
Priority to US14/521,614 priority patent/US20150041992A1/en
Priority to US16/016,329 priority patent/US10361144B2/en
Priority to US16/016,327 priority patent/US10283438B2/en
Priority to US16/016,285 priority patent/US10262923B2/en
Priority to US16/154,711 priority patent/US10312182B2/en
Priority to US16/435,143 priority patent/US10424533B1/en
Priority to US16/569,596 priority patent/US10636726B2/en
Priority to US16/665,707 priority patent/US10727166B2/en
Priority to US16/939,304 priority patent/US11205608B2/en
Priority to US17/555,795 priority patent/US20220115296A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/0538Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0552Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the device and the other elements being mounted on opposite sides of a common substrate
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1071Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02379Fan-out arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05025Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
JP2005168373A 2005-06-08 2005-06-08 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 Active JP4311376B2 (ja)

Priority Applications (21)

Application Number Priority Date Filing Date Title
JP2005168373A JP4311376B2 (ja) 2005-06-08 2005-06-08 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
US11/433,901 US7495331B2 (en) 2005-06-08 2006-05-12 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
KR1020060045642A KR20060128640A (ko) 2005-06-08 2006-05-22 반도체 장치, 반도체 장치의 제조 방법, 전자 부품, 회로기판, 및 전자 기기
EP06011084A EP1732215B1 (de) 2005-06-08 2006-05-30 Halbleiterbauelement, Herstellungsverfahren für ein Halbleiterbauelement, elektronisches Bauelement, Schaltungssubstrat, und elektronische Vorrichtung
TW095119256A TWI325686B (en) 2005-06-08 2006-05-30 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
CNA2006100887627A CN1877989A (zh) 2005-06-08 2006-06-05 半导体装置、半导体装置的制造方法、电子器件、电路基板及电子设备
US12/237,750 US8012864B2 (en) 2005-06-08 2008-09-25 Manufacturing method for interconnection having stress-absorbing layer between the semiconductor substrate and the external connection terminal
US12/947,861 US8004077B2 (en) 2005-06-08 2010-11-17 Interconnection of land section to wiring layers at center of external connection terminals in semiconductor device and manufacturing thereof
US13/185,039 US8294260B2 (en) 2005-06-08 2011-07-18 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US13/624,324 US8673767B2 (en) 2005-06-08 2012-09-21 Manufacturing method for semiconductor device
US14/156,806 US8896104B2 (en) 2005-06-08 2014-01-16 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US14/521,614 US20150041992A1 (en) 2005-06-08 2014-10-23 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/016,285 US10262923B2 (en) 2005-06-08 2018-06-22 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/016,329 US10361144B2 (en) 2005-06-08 2018-06-22 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/016,327 US10283438B2 (en) 2005-06-08 2018-06-22 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/154,711 US10312182B2 (en) 2005-06-08 2018-10-08 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/435,143 US10424533B1 (en) 2005-06-08 2019-06-07 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/569,596 US10636726B2 (en) 2005-06-08 2019-09-12 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/665,707 US10727166B2 (en) 2005-06-08 2019-10-28 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US16/939,304 US11205608B2 (en) 2005-06-08 2020-07-27 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
US17/555,795 US20220115296A1 (en) 2005-06-08 2021-12-20 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005168373A JP4311376B2 (ja) 2005-06-08 2005-06-08 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008056820A Division JP2008211806A (ja) 2008-03-06 2008-03-06 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器

Publications (2)

Publication Number Publication Date
JP2006344737A JP2006344737A (ja) 2006-12-21
JP4311376B2 true JP4311376B2 (ja) 2009-08-12

Family

ID=37103014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005168373A Active JP4311376B2 (ja) 2005-06-08 2005-06-08 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器

Country Status (6)

Country Link
US (16) US7495331B2 (de)
EP (1) EP1732215B1 (de)
JP (1) JP4311376B2 (de)
KR (1) KR20060128640A (de)
CN (1) CN1877989A (de)
TW (1) TWI325686B (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4311376B2 (ja) 2005-06-08 2009-08-12 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
US7932179B2 (en) * 2007-07-27 2011-04-26 Micron Technology, Inc. Method for fabricating semiconductor device having backside redistribution layers
US8089195B2 (en) * 2007-12-17 2012-01-03 Resonance Semiconductor Corporation Integrated acoustic bandgap devices for energy confinement and methods of fabricating same
GB0817831D0 (en) * 2008-09-30 2008-11-05 Cambridge Silicon Radio Ltd Improved packaging technology
JP2012056194A (ja) * 2010-09-09 2012-03-22 Seiko Epson Corp 圧電素子、圧電アクチュエーター、液体噴射ヘッド、および液体噴射装置
US8569861B2 (en) * 2010-12-22 2013-10-29 Analog Devices, Inc. Vertically integrated systems
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
JP2013098209A (ja) * 2011-10-28 2013-05-20 Seiko Epson Corp 回路基板、電子デバイス、電子機器、及び回路基板の製造方法
WO2014054362A1 (ja) * 2012-10-02 2014-04-10 株式会社村田製作所 電子部品及び電子モジュール
US9445536B1 (en) 2013-08-30 2016-09-13 Integrated Device Technology, Inc. Crystal oscillator fabrication methods using dual-deposition of mounting cement and dual-curing techniques
US9397151B1 (en) 2013-08-30 2016-07-19 Integrated Device Technology, Inc. Packaged integrated circuits having high-Q inductors therein and methods of forming same
JP2016058596A (ja) * 2014-09-11 2016-04-21 ソニー株式会社 電子デバイス、部品実装基板及び電子機器
CN104505385B (zh) * 2014-12-18 2018-01-19 西安紫光国芯半导体有限公司 一种半导体用通孔/接触孔
WO2017039275A1 (ko) * 2015-08-31 2017-03-09 한양대학교 산학협력단 반도체 패키지 구조체, 및 그 제조 방법
DE20168827T1 (de) 2017-06-30 2021-01-21 Gtx Medical B.V. System zur neuromodulierung
JP6635605B2 (ja) * 2017-10-11 2020-01-29 国立研究開発法人理化学研究所 電流導入端子並びにそれを備えた圧力保持装置及びx線撮像装置
US10730743B2 (en) 2017-11-06 2020-08-04 Analog Devices Global Unlimited Company Gas sensor packages
EP3653256B1 (de) 2018-11-13 2022-03-30 ONWARD Medical N.V. Steuerungssystem zur bewegungsrekonstruktion und/oder wiederherstellung für einen patienten
EP3695878B1 (de) 2019-02-12 2023-04-19 ONWARD Medical N.V. System zur neuromodulierung
US11587839B2 (en) 2019-06-27 2023-02-21 Analog Devices, Inc. Device with chemical reaction chamber
EP3827871A1 (de) 2019-11-27 2021-06-02 ONWARD Medical B.V. Neuromodulationssystem
CN113644040B (zh) * 2020-04-27 2024-03-01 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
TWI790168B (zh) * 2022-05-11 2023-01-11 天光材料科技股份有限公司 圖案化半導體層之方法

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4322778A (en) * 1980-01-25 1982-03-30 International Business Machines Corp. High performance semiconductor package assembly
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
US5028983A (en) * 1988-10-28 1991-07-02 International Business Machines Corporation Multilevel integrated circuit packaging structures
US5108541A (en) * 1991-03-06 1992-04-28 International Business Machines Corp. Processes for electrically conductive decals filled with inorganic insulator material
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US6809421B1 (en) 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JPH10321762A (ja) 1997-05-15 1998-12-04 Matsushita Electric Ind Co Ltd 半導体装置
JP3184493B2 (ja) 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US6222276B1 (en) * 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
JP3563604B2 (ja) * 1998-07-29 2004-09-08 株式会社東芝 マルチチップ半導体装置及びメモリカード
US6153929A (en) * 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
US6424048B1 (en) 1998-12-16 2002-07-23 Seiko Epson Corporation Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them
US6656828B1 (en) 1999-01-22 2003-12-02 Hitachi, Ltd. Method of forming bump electrodes
JP2000311982A (ja) 1999-04-26 2000-11-07 Toshiba Corp 半導体装置と半導体モジュールおよびそれらの製造方法
JP2001094390A (ja) 1999-09-20 2001-04-06 Toshiba Corp 弾性表面波デバイスおよびその製造方法
JP2001127243A (ja) * 1999-10-26 2001-05-11 Sharp Corp 積層半導体装置
KR100440507B1 (ko) * 2000-03-23 2004-07-15 세이코 엡슨 가부시키가이샤 반도체장치 및 그 제조방법, 회로기판 및 전자기기
JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
EP1295795B1 (de) * 2000-06-23 2010-01-13 Tetra Laval Holdings & Finance SA Verfahren und vorrichtung zum füllen, und behälter zum füllen und verpacken
ATE259949T1 (de) * 2000-06-30 2004-03-15 Doornes Transmissie Bv Stufenloses getriebe
IT1316734B1 (it) * 2000-07-07 2003-05-12 Korg Italy S P A Dispositivo elettronico avvalentesi di piu' sequecers capaci difunzionare in maniera indipendente o coordinata
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US7151036B1 (en) * 2002-07-29 2006-12-19 Vishay-Siliconix Precision high-frequency capacitor formed on semiconductor substrate
JP3864697B2 (ja) 2000-11-14 2007-01-10 セイコーエプソン株式会社 弾性表面波素子
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
JP4422323B2 (ja) * 2000-12-15 2010-02-24 株式会社ルネサステクノロジ 半導体装置
JP3535461B2 (ja) 2001-01-10 2004-06-07 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
JP2002208656A (ja) 2001-01-11 2002-07-26 Mitsubishi Electric Corp 半導体装置
KR100352236B1 (ko) 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
JP3444420B2 (ja) 2001-03-26 2003-09-08 セイコーエプソン株式会社 弾性表面波装置及びその製造方法
JP2002290184A (ja) 2001-03-28 2002-10-04 Seiko Epson Corp 弾性表面波装置及びその製造方法
JP2002359347A (ja) 2001-03-28 2002-12-13 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP4685273B2 (ja) 2001-05-31 2011-05-18 京セラキンセキ株式会社 圧電発振器とその製造方法
JP4039012B2 (ja) 2001-07-05 2008-01-30 エプソントヨコム株式会社 圧電発振器
US6696320B2 (en) * 2001-09-30 2004-02-24 Intel Corporation Low profile stacked multi-chip package and method of forming same
JP4292748B2 (ja) 2002-03-13 2009-07-08 セイコーエプソン株式会社 半導体装置の製造方法
JP2003282790A (ja) 2002-03-20 2003-10-03 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
WO2003083543A1 (fr) * 2002-04-01 2003-10-09 Ibiden Co., Ltd. Substrat support de puce a circuit integre, procede de fabrication de substrat support de puce a circuit integre, dispositif de communication optique et procede de fabrication de dispositif de communication optique
JP2003309296A (ja) 2002-04-12 2003-10-31 Nikon Corp 集積回路装置及びその製造方法、並びに、圧電振動子及びその製造方法
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
KR100484148B1 (ko) * 2002-07-27 2005-04-18 삼성전자주식회사 개선된 비트율 제어 방법과 그 장치
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
JP2004128063A (ja) 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US7030481B2 (en) * 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
JP3918794B2 (ja) * 2002-12-10 2007-05-23 セイコーエプソン株式会社 圧電発振器およびその製造方法並びに電子機器
JP4221756B2 (ja) 2002-12-27 2009-02-12 セイコーエプソン株式会社 圧電発振器およびその製造方法
JP2004235719A (ja) 2003-01-28 2004-08-19 Toyo Commun Equip Co Ltd 圧電発振器とその製造方法
JP4149289B2 (ja) 2003-03-12 2008-09-10 株式会社ルネサステクノロジ 半導体装置
JP3800335B2 (ja) 2003-04-16 2006-07-26 セイコーエプソン株式会社 光デバイス、光モジュール、半導体装置及び電子機器
JP2004327527A (ja) 2003-04-22 2004-11-18 Seiko Epson Corp 電子装置及びその製造方法並びに電子機器
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
JP2004364041A (ja) 2003-06-05 2004-12-24 Fujitsu Media Device Kk 弾性表面波デバイス及びその製造方法
US6977357B2 (en) * 2003-07-09 2005-12-20 Lincoln Global, Inc. Welding wire positioning system
JP4112448B2 (ja) 2003-07-28 2008-07-02 株式会社東芝 電気光配線基板及び半導体装置
JP4268480B2 (ja) 2003-08-27 2009-05-27 京セラ株式会社 電子部品封止用基板およびそれを用いた電子装置
JP4247611B2 (ja) 2003-09-24 2009-04-02 セイコーエプソン株式会社 半導体装置
US7081411B2 (en) 2003-10-18 2006-07-25 Northrop Grumman Corporation Wafer etching techniques
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
US7293834B2 (en) * 2004-04-21 2007-11-13 Oakworks, Inc. Articulating table
JP2006109400A (ja) 2004-09-13 2006-04-20 Seiko Epson Corp 電子部品、回路基板、電子機器、電子部品の製造方法
CN100525097C (zh) 2004-09-13 2009-08-05 精工爱普生株式会社 电子零件和电子零件的制造方法
JP4311376B2 (ja) * 2005-06-08 2009-08-12 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
JP4766143B2 (ja) * 2008-09-15 2011-09-07 株式会社デンソー 半導体装置およびその製造方法
JP5763703B2 (ja) 2013-04-24 2015-08-12 本田技研工業株式会社 自動変速機の制御装置

Also Published As

Publication number Publication date
US20090029505A1 (en) 2009-01-29
US20190295927A1 (en) 2019-09-26
US20220115296A1 (en) 2022-04-14
US10262923B2 (en) 2019-04-16
US20140131890A1 (en) 2014-05-15
US10361144B2 (en) 2019-07-23
US8004077B2 (en) 2011-08-23
US20110062566A1 (en) 2011-03-17
KR20060128640A (ko) 2006-12-14
US10283438B2 (en) 2019-05-07
US20180301394A1 (en) 2018-10-18
US20200357724A1 (en) 2020-11-12
US11205608B2 (en) 2021-12-21
US10727166B2 (en) 2020-07-28
TWI325686B (en) 2010-06-01
US10636726B2 (en) 2020-04-28
US20180301395A1 (en) 2018-10-18
US20150041992A1 (en) 2015-02-12
US8012864B2 (en) 2011-09-06
EP1732215B1 (de) 2012-03-28
US7495331B2 (en) 2009-02-24
TW200742249A (en) 2007-11-01
US10312182B2 (en) 2019-06-04
US20190043786A1 (en) 2019-02-07
US20060278983A1 (en) 2006-12-14
US20200006200A1 (en) 2020-01-02
US8673767B2 (en) 2014-03-18
US20200066616A1 (en) 2020-02-27
US10424533B1 (en) 2019-09-24
US8294260B2 (en) 2012-10-23
US20180301393A1 (en) 2018-10-18
JP2006344737A (ja) 2006-12-21
US8896104B2 (en) 2014-11-25
CN1877989A (zh) 2006-12-13
US20110266690A1 (en) 2011-11-03
EP1732215A3 (de) 2007-02-14
EP1732215A2 (de) 2006-12-13
US20130026640A1 (en) 2013-01-31

Similar Documents

Publication Publication Date Title
JP4311376B2 (ja) 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
JP2006109400A (ja) 電子部品、回路基板、電子機器、電子部品の製造方法
KR20200000058A (ko) 표면 탄성파 소자 패키지 및 그 제조 방법
JP5170282B2 (ja) 電子部品の製造方法
JP5569473B2 (ja) 電子部品、回路基板及び電子機器
JP2008211806A (ja) 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
JP5516511B2 (ja) 電子部品、回路基板及び電子機器
JP5773027B2 (ja) 電子部品及び電子機器
WO2018221172A1 (ja) フィルタ装置

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070913

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071009

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071210

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080306

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090421

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090504

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120522

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4311376

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130522

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140522

Year of fee payment: 5

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250