JP4237203B2 - 不定形高電子移動度トランジスタの製造方法 - Google Patents
不定形高電子移動度トランジスタの製造方法 Download PDFInfo
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- JP4237203B2 JP4237203B2 JP2006170476A JP2006170476A JP4237203B2 JP 4237203 B2 JP4237203 B2 JP 4237203B2 JP 2006170476 A JP2006170476 A JP 2006170476A JP 2006170476 A JP2006170476 A JP 2006170476A JP 4237203 B2 JP4237203 B2 JP 4237203B2
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- 238000000034 method Methods 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 230000001681 protective effect Effects 0.000 claims description 31
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 6
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229920001577 copolymer Polymers 0.000 claims description 3
- 235000001674 Agaricus brunnescens Nutrition 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 90
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 21
- 125000006850 spacer group Chemical group 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 210000002414 leg Anatomy 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
以下で説明する実施例は、当業者に本発明の思想が十分に伝達され得るようにするために一例として提示されるものである。したがって、本発明は、以下で説明する実施例に限らず、様々な変形が可能である。なお、図面において、或る層が他の層上に位置すると記述されている場合、他の層上に直接に形成されることができ、又はそれらの間に第3の層が介在されることもできる。また、図面で、各層の厚さや大きさは、説明の便宜及び明確を図るために、誇張して図示している。なお、本明細書において、同一の参照番号は、同一の構成要素を示している。
2,22 チャンネル層
3 AlGaAsスペーサ層
4 Siデルタドーピング層
5 n−AlGaAs層
6 エッチング停止層
7 n−GaAs層
8 GaAsキャップ層
9,25 ソース電極
10,26 ドレイン電極
11,34 ゲート電極
21 バッファ層
21a GaAs層
21b AlGaAs/GaAs超格子層
21c AlGaAs層
21d,23b Si面ドーピング層
21e,23a AlGaAsスペーサ層
23c AlGaAsショットキー層
24 キャップ層
27 第1保護膜
28,30乃至33 感光膜
29 第2保護膜
Claims (9)
- チャンネル層を有するGaAs基板の最上部にキャップ層を形成する段階と、
前記キャップ層上の両側部の各々にソース電極及びドレイン電極を形成する段階と、
上部面の全体に第1保護膜を形成した後、上部面の全体に開口幅W1を有する感光層を形成する段階と、
前記キャップ層が露出するように前記第1保護膜をパターニングする段階と、
前記感光層をマスクとしてドライエッチング方法で露出した部分の前記キャップ層を除去して前記GaAs基板を露出させ、前記幅W1の第1リセス構造を形成する段階と、
上部面の全体に第2保護膜を形成した後、前記第1リセス構造内の前記GaAs基板が露出するように前記第2保護膜をパターニングして、前記第1リセス構造の幅W1より狭い幅W2を有する第2リセス構造を形成する段階と、
上部面の全体に多層構造の感光膜を形成した後、前記第2リセス構造を介して前記GaAs基板が露出し、ゲート電極の形状で、前記第2リセス構造の幅W2よりも広くかつ前記第1リセス構造の幅W1よりも狭い幅W3を有する開口部を有するように、前記多層構造の感光膜をパターニングする段階と、
前記GaAs基板の最上部の一部をエッチングして前記第2リセス構造の幅W2と同じ幅を有する第3リセス構造を形成する段階と、
前記開口部が埋め込まれるように金属を蒸着した後、前記多層構造の感光膜を除去して、前記第2リセス構造及び前記第3リセス構造を介して前記GaAs基板に連結される前記ゲート電極を形成する段階と
を有することを特徴とする不定形高電子移動度トランジスタの製造方法。 - 前記第1及び第2保護膜は、シリコン窒化膜又はシリコン酸化膜で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1及び第2保護膜は、非等方性エッチング方法でパターニングすることを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1及び第2保護膜は、200乃至500Åの厚さで形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1リセス構造の幅は、0.5乃至0.8μm、前記第2リセス構造の幅は、0.1乃至0.15μmとなるようにすることを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜は、PMMA/コポリマー/PMMA構造で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記ゲート電極の形状の開口部は、T字状又はキノコ形状で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜をパターニングする段階を進行した後、前記開口部を介して露出する前記基板の厚さの一部をエッチングする段階をさらに有することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜は、リフト−オフ方法で除去することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
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KR1020050084755A KR100631051B1 (ko) | 2005-09-12 | 2005-09-12 | 부정형 고 전자 이동도 트랜지스터의 제조 방법 |
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JP2007081371A JP2007081371A (ja) | 2007-03-29 |
JP4237203B2 true JP4237203B2 (ja) | 2009-03-11 |
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US (1) | US7419862B2 (ja) |
JP (1) | JP4237203B2 (ja) |
KR (1) | KR100631051B1 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7534672B1 (en) | 2006-09-08 | 2009-05-19 | Hrl Laboratories, Llc | Tiered gate device with source and drain extensions |
US7608497B1 (en) | 2006-09-08 | 2009-10-27 | Ivan Milosavljevic | Passivated tiered gate structure transistor and fabrication method |
KR100795242B1 (ko) * | 2006-11-03 | 2008-01-15 | 학교법인 포항공과대학교 | 반도체 소자의 게이트 형성 방법 및 그 게이트 구조 |
JP5114947B2 (ja) | 2006-12-28 | 2013-01-09 | 富士通株式会社 | 窒化物半導体装置とその製造方法 |
JP5186776B2 (ja) * | 2007-02-22 | 2013-04-24 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP2009302166A (ja) * | 2008-06-11 | 2009-12-24 | Panasonic Corp | 半導体装置およびその製造方法 |
JP5564815B2 (ja) * | 2009-03-31 | 2014-08-06 | サンケン電気株式会社 | 半導体装置及び半導体装置の製造方法 |
KR101243836B1 (ko) | 2009-09-04 | 2013-03-20 | 한국전자통신연구원 | 반도체 소자 및 그 형성 방법 |
JP2011124246A (ja) * | 2009-12-08 | 2011-06-23 | Mitsubishi Electric Corp | ヘテロ接合電界効果型トランジスタ及びその製造方法 |
CN102315262B (zh) * | 2010-07-06 | 2013-11-20 | 西安能讯微电子有限公司 | 半导体器件及其制造方法 |
JP5636867B2 (ja) * | 2010-10-19 | 2014-12-10 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5685918B2 (ja) * | 2010-12-10 | 2015-03-18 | 富士通株式会社 | 半導体装置の製造方法 |
KR101729653B1 (ko) | 2013-12-30 | 2017-04-25 | 한국전자통신연구원 | 질화물 반도체 소자 |
JP2017168768A (ja) * | 2016-03-18 | 2017-09-21 | 三菱電機株式会社 | 電界効果トランジスタおよびその製造方法 |
CN108695157B (zh) * | 2018-04-16 | 2020-09-04 | 厦门市三安集成电路有限公司 | 一种空隙型复合钝化介质的氮化镓晶体管及制作方法 |
WO2020214227A2 (en) | 2019-04-04 | 2020-10-22 | Hrl Laboratories, Llc | Miniature field plate t-gate and method of fabricating the same |
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JP2978972B2 (ja) * | 1992-03-12 | 1999-11-15 | 富士通株式会社 | 半導体装置の製造方法 |
JPH07335669A (ja) | 1994-06-06 | 1995-12-22 | Murata Mfg Co Ltd | 半導体装置の製造方法 |
JPH0936133A (ja) | 1995-07-14 | 1997-02-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5698870A (en) * | 1996-07-22 | 1997-12-16 | The United States Of America As Represented By The Secretary Of The Air Force | High electron mobility transistor (HEMT) and pseudomorphic high electron mobility transistor (PHEMT) devices with single layer integrated metal |
JP3612533B2 (ja) | 1996-10-29 | 2005-01-19 | 株式会社デンソー | 半導体装置の製造方法 |
JPH11162945A (ja) | 1997-12-02 | 1999-06-18 | Fujitsu Ltd | ドライエッチング方法 |
EP0974160A1 (en) * | 1998-02-09 | 2000-01-26 | Koninklijke Philips Electronics N.V. | Process of manufacturing a semiconductor device including a buried channel field effect transistor |
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JP2003059949A (ja) | 2001-08-20 | 2003-02-28 | Nec Corp | 電界効果トランジスタ及び電界効果トランジスタの製造方法 |
US6838325B2 (en) * | 2002-10-24 | 2005-01-04 | Raytheon Company | Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor |
JP4064800B2 (ja) | 2002-12-10 | 2008-03-19 | 株式会社東芝 | ヘテロ接合型化合物半導体電界効果トランジスタ及びその製造方法 |
JP4371668B2 (ja) * | 2003-02-13 | 2009-11-25 | 三菱電機株式会社 | 半導体装置 |
TW569077B (en) * | 2003-05-13 | 2004-01-01 | Univ Nat Chiao Tung | Method for fabricating nanometer gate in semiconductor device using thermally reflowed resist technology |
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KR100631051B1 (ko) | 2006-10-04 |
US20070134862A1 (en) | 2007-06-14 |
JP2007081371A (ja) | 2007-03-29 |
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