JP2007081371A - 不定形高電子移動度トランジスタの製造方法 - Google Patents
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
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- 230000015556 catabolic process Effects 0.000 abstract description 4
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- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 21
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 18
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- 238000001312 dry etching Methods 0.000 description 8
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
【解決手段】キャップ層24が形成された基板を用意し、キャップ層24上にソース電極25及びドレイン電極26を形成し、第1保護膜27を形成した後、キャップ層24が露出するように第1保護膜27をパターニングし、そのキャップ層24を除去して、第1リセス構造を形成し、第2保護膜29を形成した後、基板が露出するように第2保護膜29をパターニングして、第2リセス構造を形成し、感光膜31,32,33を形成した後、基板20が露出し、ゲート電極の形状の開口部を有するように感光膜31,32,33をパターニングし、開口部が埋め込まれるように金属を蒸着した後、感光膜31,32,33を除去して、基板20に連結されるゲート電極34を形成する。
【選択図】図2k
Description
以下で説明する実施例は、当業者に本発明の思想が十分に伝達され得るようにするために一例として提示されるものである。したがって、本発明は、以下で説明する実施例に限らず、様々な変形が可能である。なお、図面において、或る層が他の層上に位置すると記述されている場合、他の層上に直接に形成されることができ、又はそれらの間に第3の層が介在されることもできる。また、図面で、各層の厚さや大きさは、説明の便宜及び明確を図るために、誇張して図示している。なお、本明細書において、同一の参照番号は、同一の構成要素を示している。
2,22 チャンネル層
3 AlGaAsスペーサ層
4 Siデルタドーピング層
5 n−AlGaAs層
6 エッチング停止層
7 n−GaAs層
8 GaAsキャップ層
9,25 ソース電極
10,26 ドレイン電極
11,34 ゲート電極
21 バッファ層
21a GaAs層
21b AlGaAs/GaAs超格子層
21c AlGaAs層
21d,23b Si面ドーピング層
21e,23a AlGaAsスペーサ層
23c AlGaAsショットキー層
24 キャップ層
27 第1保護膜
28,30乃至33 感光膜
29 第2保護膜
Claims (9)
- チャンネル層を有し、最上部にキャップ層が形成された基板を提供する段階と、
前記キャップ層上にソース電極及びドレイン電極を形成する段階と、
上部面の全体に第1保護膜を形成した後、チャンネル領域の前記キャップ層が露出するように前記第1保護膜をパターニングする段階と、
露出した部分の前記キャップ層を除去して、第1リセス構造を形成する段階と、
上部面の全体に第2保護膜を形成した後、前記第1リセス構造内の前記基板が露出するように前記第2保護膜をパターニングして、第2リセス構造を形成する段階と、
上部面の全体に多層構造の感光膜を形成した後、前記第2リセス構造を介して前記基板が露出し、ゲート電極の形状の開口部を有するように、前記多層構造の感光膜をパターニングする段階と、
前記開口部が埋め込まれるように金属を蒸着した後、前記多層構造の感光膜を除去して、前記第2リセス構造を介して前記基板に連結される前記ゲート電極を形成する段階と
を有することを特徴とする不定形高電子移動度トランジスタの製造方法。 - 前記第1及び第2保護膜は、シリコン窒化膜又はシリコン酸化膜で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1及び第2保護膜は、非等方性エッチング方法でパターニングすることを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1及び第2保護膜は、200乃至500Åの厚さで形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記第1リセス構造の幅は、0.5乃至0.8μm、前記第2リセス構造の幅は、0.1乃至0.15μmとなるようにすることを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜は、PMMA/コポリマー/PMMA構造で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記ゲート電極の形状の開口部は、T字状又はキノコ形状で形成することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜をパターニングする段階を進行した後、前記開口部を介して露出する前記基板の厚さの一部をエッチングする段階をさらに有することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
- 前記多層構造の感光膜は、リフト−オフ方法で除去することを特徴とする請求項1に記載の不定形高電子移動度トランジスタの製造方法。
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KR1020050084755A KR100631051B1 (ko) | 2005-09-12 | 2005-09-12 | 부정형 고 전자 이동도 트랜지스터의 제조 방법 |
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JP2007081371A true JP2007081371A (ja) | 2007-03-29 |
JP4237203B2 JP4237203B2 (ja) | 2009-03-11 |
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JP2006170476A Expired - Fee Related JP4237203B2 (ja) | 2005-09-12 | 2006-06-20 | 不定形高電子移動度トランジスタの製造方法 |
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US (1) | US7419862B2 (ja) |
JP (1) | JP4237203B2 (ja) |
KR (1) | KR100631051B1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011124246A (ja) * | 2009-12-08 | 2011-06-23 | Mitsubishi Electric Corp | ヘテロ接合電界効果型トランジスタ及びその製造方法 |
CN102315262A (zh) * | 2010-07-06 | 2012-01-11 | 西安能讯微电子有限公司 | 半导体器件及其制造方法 |
JP2017168768A (ja) * | 2016-03-18 | 2017-09-21 | 三菱電機株式会社 | 電界効果トランジスタおよびその製造方法 |
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US7534672B1 (en) | 2006-09-08 | 2009-05-19 | Hrl Laboratories, Llc | Tiered gate device with source and drain extensions |
US7608497B1 (en) | 2006-09-08 | 2009-10-27 | Ivan Milosavljevic | Passivated tiered gate structure transistor and fabrication method |
KR100795242B1 (ko) * | 2006-11-03 | 2008-01-15 | 학교법인 포항공과대학교 | 반도체 소자의 게이트 형성 방법 및 그 게이트 구조 |
JP5114947B2 (ja) | 2006-12-28 | 2013-01-09 | 富士通株式会社 | 窒化物半導体装置とその製造方法 |
JP5186776B2 (ja) * | 2007-02-22 | 2013-04-24 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP2009302166A (ja) * | 2008-06-11 | 2009-12-24 | Panasonic Corp | 半導体装置およびその製造方法 |
JP5564815B2 (ja) * | 2009-03-31 | 2014-08-06 | サンケン電気株式会社 | 半導体装置及び半導体装置の製造方法 |
KR101243836B1 (ko) | 2009-09-04 | 2013-03-20 | 한국전자통신연구원 | 반도체 소자 및 그 형성 방법 |
JP5636867B2 (ja) * | 2010-10-19 | 2014-12-10 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5685918B2 (ja) * | 2010-12-10 | 2015-03-18 | 富士通株式会社 | 半導体装置の製造方法 |
KR101729653B1 (ko) | 2013-12-30 | 2017-04-25 | 한국전자통신연구원 | 질화물 반도체 소자 |
CN108695157B (zh) * | 2018-04-16 | 2020-09-04 | 厦门市三安集成电路有限公司 | 一种空隙型复合钝化介质的氮化镓晶体管及制作方法 |
EP3948955A4 (en) * | 2019-04-04 | 2023-05-10 | HRL Laboratories, LLC | MINIATURE FIELD PLATE T-GRID AND METHOD OF MAKING IT |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011124246A (ja) * | 2009-12-08 | 2011-06-23 | Mitsubishi Electric Corp | ヘテロ接合電界効果型トランジスタ及びその製造方法 |
CN102315262A (zh) * | 2010-07-06 | 2012-01-11 | 西安能讯微电子有限公司 | 半导体器件及其制造方法 |
JP2017168768A (ja) * | 2016-03-18 | 2017-09-21 | 三菱電機株式会社 | 電界効果トランジスタおよびその製造方法 |
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US20070134862A1 (en) | 2007-06-14 |
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