JP4191202B2 - 不揮発性記憶素子を搭載した半導体記憶装置 - Google Patents
不揮発性記憶素子を搭載した半導体記憶装置 Download PDFInfo
- Publication number
- JP4191202B2 JP4191202B2 JP2006121962A JP2006121962A JP4191202B2 JP 4191202 B2 JP4191202 B2 JP 4191202B2 JP 2006121962 A JP2006121962 A JP 2006121962A JP 2006121962 A JP2006121962 A JP 2006121962A JP 4191202 B2 JP4191202 B2 JP 4191202B2
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- Prior art keywords
- voltage
- antifuse
- circuit
- power supply
- nonvolatile memory
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Description
02、12、22、32、42 AF電源昇圧回路
03、13、23、33、43、53 書き込み選択信号
04、14、24、34、44、54 プリセット制御信号
05、15、25、35、45、55 判定信号
06、16、26、36、46、56 アンチヒューズ判定接点
27、37 AF電源VB昇圧回路
100、110、120、130、140、150 アンチヒューズ(AF)書き込み回路
Claims (9)
- 第1の不揮発性記憶素子と、
第2の不揮発性記憶素子と、
前記第1の不揮発性記憶素子に書き込み電圧を印加するための第1の電圧供給部と、
前記第2の不揮発性記憶素子に書き込み電圧を印加するための第2の電圧供給部と、
を備えており、
前記第1の不揮発性記憶素子に書き込み電圧を印加するために前記第1の電圧供給部に対して供給される電源電圧が、前記第2の不揮発性記憶素子に書き込み電圧を印加するために前記第2の電圧供給部に対して供給される電源電圧よりも低く設定されていることを特徴とする半導体記憶装置。 - 前記第1の電圧供給部は、前記第1の不揮発性記憶素子の一端の電極に電圧を供給する第1の昇圧回路を備えており、
前記第2の電圧供給部は、前記第2の不揮発性記憶素子の一端の電極に電圧を供給する第2の昇圧回路を備えており、
前記第1の昇圧回路の電源電圧に対する昇圧係数は、前記第2の昇圧回路の電源電圧に対する昇圧係数よりも大きいことを特徴とする請求項1に記載の半導体記憶装置。 - 前記第1及び前記第2の不揮発性記憶素子の他端の電極には、共通の電圧を印加していることを特徴とする請求項2に記載の半導体記憶装置。
- 前記第1の電圧供給部は、前記第1の不揮発性記憶素子の他端の電極に前記第1の昇圧回路と反対極性の電圧を供給する第3の昇圧回路を備えており、
前記第2の電圧供給部は、前記第2の不揮発性記憶素子の他端の電極に前記第2の昇圧回路と反対極性の電圧を供給する第4の昇圧回路を備えており、
前記第3の昇圧回路の電源電圧に対する昇圧係数は、前記第4の昇圧回路の電源電圧に対する昇圧係数よりも大きいことを特徴とする請求項2に記載の半導体記憶装置。 - 前記第1の電圧供給部は、前記第1の不揮発性記憶素子の一端の電極に電圧を供給する第1の昇圧回路を備えており、
前記第2の電圧供給部は、前記第2の不揮発性記憶素子の一端の電極に電圧を供給する第2の昇圧回路を備えており、
前記第1の昇圧回路の電源電圧に対する昇圧係数と前記第2の昇圧回路の電源電圧に対する昇圧係数とは等しく、
前記第1の不揮発性記憶素子の他端の電極に供給する電圧は、前記第2の不揮発性記憶素子の他端の電極に供給する電圧よりも低いことを特徴とする請求項1に記載の半導体記憶装置。 - 前記第1及び第2の不揮発性記憶素子は、同一構成のアンチヒューズであることを特徴とする請求項1乃至5のいずれか1項に記載の半導体記憶装置。
- 前記昇圧回路の少なくとも1つは、半導体記憶装置の内部回路に使用される昇圧回路と共有していることを特徴とする請求項2乃至6のいずれか1項に記載の半導体記憶装置。
- 前記第1の不揮発性記憶素子は、冗長回路の不良アドレス置換用であり、
前記第2の不揮発性記憶素子は、内部動作切り替え用と冗長回路の不良アドレス置換用であることを特徴とする請求項1乃至7のいずれか1項に記載の半導体記憶装置。 - 前記第1の電圧供給部は、供給される電源電圧が低いモジュールテストにおける不揮発性記憶素子の書き込みに使用され、前記第2の電圧供給部は、供給される電源電圧が高いウェハテストやパッケージテストで使用されることを特徴とする請求項1乃至8のいずれか1項に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006121962A JP4191202B2 (ja) | 2006-04-26 | 2006-04-26 | 不揮発性記憶素子を搭載した半導体記憶装置 |
TW096113190A TWI340390B (en) | 2006-04-26 | 2007-04-14 | Semiconductor memory device comprising memory element programming circuits having different programming threshold power supply voltages |
US11/790,200 US7706166B2 (en) | 2006-04-26 | 2007-04-24 | Semiconductor memory device comprising memory element programming circuits having different programming threshold power supply voltages |
Applications Claiming Priority (1)
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---|---|---|---|
JP2006121962A JP4191202B2 (ja) | 2006-04-26 | 2006-04-26 | 不揮発性記憶素子を搭載した半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007294031A JP2007294031A (ja) | 2007-11-08 |
JP4191202B2 true JP4191202B2 (ja) | 2008-12-03 |
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Country Status (3)
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---|---|
US (1) | US7706166B2 (ja) |
JP (1) | JP4191202B2 (ja) |
TW (1) | TWI340390B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101102776B1 (ko) * | 2008-02-13 | 2012-01-05 | 매그나칩 반도체 유한회사 | 비휘발성 메모리 소자의 단위 셀 및 이를 구비한 비휘발성메모리 소자 |
KR101137871B1 (ko) * | 2010-03-29 | 2012-04-18 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 구동 방법 |
FR3058567B1 (fr) * | 2016-11-08 | 2019-01-25 | Stmicroelectronics (Rousset) Sas | Circuit integre comportant une structure antifusible, et procede de realisation |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH02179264A (ja) | 1988-12-28 | 1990-07-12 | Nec Corp | 昇圧回路 |
US5812477A (en) * | 1996-10-03 | 1998-09-22 | Micron Technology, Inc. | Antifuse detection circuit |
US6606267B2 (en) * | 1998-06-23 | 2003-08-12 | Sandisk Corporation | High data rate write process for non-volatile flash memories |
KR100359855B1 (ko) | 1998-06-30 | 2003-01-15 | 주식회사 하이닉스반도체 | 가변전압발생기를이용한앤티퓨즈의프로그래밍회로 |
JP2004022736A (ja) | 2002-06-14 | 2004-01-22 | Nec Electronics Corp | 不揮発性ラッチ回路および半導体装置 |
JP4108519B2 (ja) | 2003-03-31 | 2008-06-25 | エルピーダメモリ株式会社 | 制御回路、半導体記憶装置、及び制御方法 |
US6690597B1 (en) * | 2003-04-24 | 2004-02-10 | Hewlett-Packard Development Company, L.P. | Multi-bit PROM memory cell |
KR100512178B1 (ko) * | 2003-05-28 | 2005-09-02 | 삼성전자주식회사 | 플렉서블한 열 리던던시 스킴을 갖는 반도체 메모리 장치 |
KR100702004B1 (ko) * | 2004-08-02 | 2007-03-30 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 비트 라인 센싱 방법 |
KR100645055B1 (ko) * | 2004-10-28 | 2006-11-10 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 방법 |
US7339848B1 (en) * | 2005-11-03 | 2008-03-04 | Cypress Semiconductor Corporation | Anti-fuse latch circuit and method including self-test |
-
2006
- 2006-04-26 JP JP2006121962A patent/JP4191202B2/ja active Active
-
2007
- 2007-04-14 TW TW096113190A patent/TWI340390B/zh active
- 2007-04-24 US US11/790,200 patent/US7706166B2/en active Active
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Publication number | Publication date |
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US20070253236A1 (en) | 2007-11-01 |
TWI340390B (en) | 2011-04-11 |
US7706166B2 (en) | 2010-04-27 |
TW200802391A (en) | 2008-01-01 |
JP2007294031A (ja) | 2007-11-08 |
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