TWI281671B - An option fuse circuit using standard CMOS manufacturing process - Google Patents

Abstract

An option fuse circuit using standard CMOS manufacturing process. The option fuse circuit contains a latch for latching signals, which includes a first endpoint and a second endpoint. The option fuse circuit also contains a comparator, which includes two input nodes and an output node. The comparator is inputted at the two input nodes with signals from the first and the second endpoints, and compares the two signals in order to output a comparison signal. The option fuse circuit further contains two logic cells for storing non-volatile data. The logic cell includes a word line end and a bit line end. The word line ends are electrically connected to the output end of the comparator, while the bit line ends are electrically connected to the first and the second endpoints, respectively.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a selective fuse circuit, and more particularly to a selection fuse circuit using a standard complementary metal oxide semiconductor process. Prior art

Among the various electronic products currently on the market, memory (such as ROM, DRAM, and SRAM) has always been one of the most important components, and it functions as a volatile and non-volatile material in electronic products. A memory includes a plurality of memory cells (Memory Cel 1), each memory cell is used to store a bit of bit data, and the plurality of memory cells are usually in an array (Array The arrangement is in the form of an integrated circuit using a semiconductor process.

In the general semiconductor process, since the yield is usually not 100%, in the manufacturing process of the integrated circuit, a certain proportion of defective products can be expected to be generated, and thus the integrated circuit is manufactured to shipped. In the process of product testing, the steps of product testing are very important and indispensable. Only through the process of product testing can products that are incomplete or unusable due to insufficient yield in the semiconductor process be screened out and eliminated. Ensure that the customer gets what works for the product at the time of shipment. It can be seen that product testing is very heavy in the semiconductor manufacturing process.

Page 6 1281671 V. Description of invention (2) One of the required processes.

Since the memory contains a very large number of memory cells (the current memory capacity is mostly tens to hundreds of millions of bytes (Mbyte), such as 64M, 1 28M, etc.), so there are so many In a memory unit, the probability of failure of at least one memory unit is very high, and if only one memory unit in a memory fails, the memory is regarded as a defective product and causes it to be unusable. As a result, memory manufacturers will be greatly troubled. Therefore, in the design of general memory, a set of spare memory cells (Redundancy Cell) is usually added in addition to the original memory cell array, and a special circuit configuration design is used to control and select the group. A connection between the alternate memory unit and the array of memory cells. With this design, it is found in the product testing process that when a memory unit at a certain location in the memory cell array fails, the special circuit configuration can be used to control the set of spare memory cells. Replacing the original function of the failed memory unit, so that the memory is not scrapped due to a few parts of the failure, thus saving a lot of cost. This special circuit configuration is generally referred to as the Option Fuse Circuit.

Referring to FIG. 1, FIG. 1 shows a conventional intention of selecting a fuse circuit 10. The selection fuse circuit 10 includes a P-type metal oxide layer semiconductor transistor 1, a P-type metal oxide layer semiconductor transistor 14, an N-type metal oxide layer semiconductor transistor 16 and a selection fuse 18. Transistor 14 and electro-crystal

Page 7 1281671 V. INSTRUCTIONS (3) The body 1 is electrically connected to each other to form an inverter, wherein the two gates are connected to be the input end of the inverter, and the two poles are connected to be the reverser. The output. One end of the transistor 12 and one end of the selection fuse 18 are electrically connected to the input end of the inverter, and the gate of the transistor 12 is electrically connected to the output end of the inverter, and the output end That is, as one of the output terminals Vout of the selection fuse circuit 10. Finally, the sources of the transistors 12, 14 are electrically coupled to a system voltage Vdd, and the source of the transistor 16 and the other end of the selected fuse 18 are electrically coupled to the ground voltage Vss. Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a schematic diagram showing the layout of the fuse 14 in FIG. Usually, the fuse 18 is selected by using a metal line segment or a poly line segment, and the fuse 18 can be selected to be burned by a laser as needed during the product testing phase, as shown in Fig. 2B. It is shown that, since the selection fuse circuit 10 is not blown when the selection fuse 18 is not blown, the signal value outputted by the output terminal vout is different (take the fuse circuit 1 shown in FIG. 1 as an example). When the selection fuse 1 8 has not been blown, Vou emits a signal π 1 ”, that is, a high potential, and when the selection fuse 18 is blown, v〇ut outputs a signal "0 π, that is, a low potential In the circuit design of a memory, the output signal values of the plurality of selected melting circuit 10 can be used to encode the memory of the memory cell array in which the memory cells of the group are replaced. Unit. However, due to the choice of the dissolved wire 18 in the layout of the day, it is usually necessary to reserve enough space in a certain area around it (as shown in Figure 2, Figure 2, reserved

1281671 V. Description of invention (4)

A space of 5//mx 5//m) to prevent damage to the surrounding components during laser blow and for laser blowout, the oxide layer of the surface needs to be hollowed out to select one of the fuses 18 Opening, however, this opening will cause moisture to penetrate and corrode, thereby destroying other components and reducing the reliability of the surrounding components. This phenomenon is related to the memory capacity of the selected fuse circuit 10 in a memory. The increase is most pronounced as the increase is greater, as more and more fuse circuits 10 represent more reserved openings, thereby increasing the chances of contamination of the various components in the memory. On the other hand, since the laser blow is relatively a time consuming process, the test process takes a long time because the blow fuses must be selected one by one in a large number of tests. In order to avoid the above problems caused by the use of the electric blowout technique in the fuse circuit technology, the prior art also utilizes a non-volatile flash memory with a suitable circuit design to achieve the same purpose. However, since flash memory cannot be fabricated using a method compatible with a standard complementary metal oxide semiconductor process, a layer of polysilicon must be used in the process, thereby increasing manufacturing costs. Summary of the invention

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a selective fuse circuit using a standard complementary metal oxide semiconductor process, using only one layer of polysilicon layer in the process, and eliminating the need for laser burnout techniques to address the above reliability.

Page 9 1281671 V. INSTRUCTIONS (5) Reduced degree, lengthy test time, and increased manufacturing costs. According to the patent application scope of the present invention, a selective fuse circuit is disclosed, which is fabricated by a standard complementary metal oxide semiconductor process technology. The select fuse circuit includes a latch including a first end point and a a second end of the signal for latching the first and second end points; a comparator comprising a second input end and an output end, the two input ends being electrically connected to the first and second end points respectively The comparator is configured to input the signals of the first and second terminals respectively at the two input ends, and compare the two signals to output a comparison signal at the output end; a first logic unit for storing one Non-volatile data, the first logic unit includes a first word line end and a first bit line end, the first word line end is electrically connected to the output end of the comparator to input the comparison signal, The first bit line end is electrically connected to the first end point; and a second logic unit is configured to store a non-volatile data, the second logic unit includes a second word line end and a first Two bit line end, the first The binary word line end is electrically connected to the output end of the comparator to input the comparison signal, and the second bit line end is electrically connected to the second end. The selective fuse circuit of the present invention utilizes a standard complementary metal Oxide semiconductor process technology manufacturing, it is very suitable for the general memory process, only need to use a layer of polysilicon layer in the process, so it can avoid the problem of the conventional technology to increase the manufacturing cost due to the use of flash memory, and the choice of the present invention The fuse circuit uses two logic units to store non-volatile data to replace the habit

Page 10 1281671 V. INSTRUCTIONS (6) In the prior art, the method of determining the value of the output signal is determined according to the state of the selected fuse, so that the reliability reduction and test time caused by the use of the laser burnout technique do not occur. Too long a problem. Embodiments Referring to Figure 3, a schematic diagram of the selected fuse circuit 20 of the present invention is shown in Figure 3. The fuse circuit 20 includes a latch 22 including a first end point N and a second end point ZN for latching the signals of the first and second terminals N, ZN; a comparator (Comparator)

24, comprising two input ends and one output end, the two input ends are respectively electrically connected to the first and second end points N, ZN, and the comparator 24 is configured to input the first and second respectively on the two input ends Signals of the endpoints N and ZN, and comparing the two signals to output a comparison signal WL at the output; - a first logic unit (Logic Cel 1) 26 for storing a non-volatile data, the first logic

The unit 26 includes a first word line terminal WL1 and a first bit line (Bit L ine) end BL1, and the first word line end WL1 is electrically connected to the output of the comparator 24. The comparison signal WL is input, and the first bit line end BL1 is electrically connected to the first end point N; and a second logic unit 28 is configured to store a non-volatile material, and the second logic unit 28 includes a first The second word line end WL2 and the second bit line end BL2, the second word line end WL2 is electrically connected to the output end of the comparator 24 to input the comparison signal WL, and the second bit line end BL2 is electrically connected. To the second endpoint ZN. Please note that the latches 22 are usually formed by mutually inverting the two inverters as shown in FIG. Next will

Page 11 1281671 V. INSTRUCTION DESCRIPTION (7) The principle of operation of selecting the fuse circuit 20 will be described in detail using a preferred embodiment of the present invention. Referring to FIG. 4 and FIG. 5, FIG. 4 is a schematic diagram showing the selection of the fuse circuit 30 as an embodiment of the present invention, wherein the connection between the components is the same as the selection of the fuse circuit 20, so there is no need to repeat the description. . As shown in FIG. 4, the selection fuse circuit 30 includes a latch 32, wherein a P-type metal oxide semiconductor transistor 42 and an N-type metal oxide semiconductor transistor 46 form an inverter. And a P-type metal oxide semiconductor transistor 44 and an N-type metal oxide semiconductor transistor 48 form another inverter, the two inverters are connected in anti-phase and with their two outputs as the first And a second endpoint N, ZN. The selection of the melting circuit 30 also includes a comparator 34. As shown in FIG. 4, the comparator 34 compares the signals input from the first and second terminals N, ZN with a plurality of logic gates for its output. A comparison signal ZWL is generated. The comparator 34 also includes a mode selection input terminal ZPGM for determining whether the selection fuse circuit 30 is in the write mode (Program Mode) or in the read mode (Read Mode); - the data is written to the input terminal DB, It is used to input the data to be written when the selection fuse circuit 30 is in the write mode. The selection fuse circuit 30 further includes a first logic unit 36 and a second logic unit 3 8 which are identical to the selection fuse circuit 20 shown in FIG. 3, and the logic unit 3 6 and 38 are used to store non- The volatile data has its word line terminal electrically connected to the output terminal of the comparator 34 for inputting the comparison signal ZWL, and its bit line terminal is electrically connected to the first and second terminals N, ZN, respectively. In this embodiment,

Page 12 1281671 V. Description of the Invention (8) The first logic unit 3 6 and the second logic unit 3 8 use a one-time programmable logic unit 40 (One-Time Programmable Cell) as shown in FIG. The second programmable logic soap element 40 includes a first transistor 5 2 and a second transistor 5 4 , wherein the first and second transistors 5 2, 5 4 are P-type metal oxide semiconductor transistors, The source of a transistor 52 is electrically connected to a power supply voltage V cc , and the gate of the first transistor 52 is used as the word line end of the logic unit 36, 38 (the connection to the comparison signal ZWL in FIG. The drain of the first transistor 52 is electrically connected to the source of the second transistor 504. The gate of the first transistor 504 is floating, and the second cymbal is connected. , 2 4 is not the pole as the logical unit 3 6 , 3 8 of the bit line end (Figure 5 = marked). The single-programmable logic unit 4 changes the input signal value of the pre-element end and the bit line end to change the number of electron charges stored in the gate of the second transistor 54 to change. The purpose of storing the data in a single programmable logic unit. - Selecting the filament circuit 3 further includes an initial module electrically coupled to the first jth f logic 36, 38 for writing data to the first and a logic unit 36, 38 in the write mode. As shown in FIG. 4, the initial module includes a first initial transistor 56 and a second initial transistor 58. The first and first initial transistors 56 and 58 are N-type metal oxide semiconductors. The crystal, ^ is electrically connected to the bit line ends of the first and second logic units 36, 38 respectively, the source of which is electrically connected to a ground voltage V ss ( 〇 v), and the comparator 34 is separately packaged ^The initial output terminals 81^, 2610 having opposite phases are electrically connected to the gates of the first and second initial transistors 56, 58 respectively for control

Page 13 1281671 V. DESCRIPTION OF THE INVENTION (9) The first and second initial transistors 5, 5, 8 are turned on to write the data into the first and second logic units 36, 38. Next, the operation of the selection fuse circuit 30 in the present embodiment in the write mode and the read mode will be described in detail. In the process of product testing, if the tester finds that certain memory cells in a memory cell array have failed, the tester writes a plurality of selected fuse circuits in the memory. The incoming action replaces the failed memory unit by selecting a plurality of spare memory units pre-placed in the memory. Here, one of the plurality of selected fuse circuits is taken as an example, and the use of FIG. The principle of operation of the fuse circuit 30 for its write mode is selected. When the fuse circuit 30 is selected for data writing, the mode selection input terminal ZPGM inputs a low voltage (0V) (ie, the selection fuse circuit 30 is in the write mode), and is input to the data input input terminal DB. To write the data of the first and second logic units 3 6 and 38, it is assumed that the data is π 0 ", the initial output terminal BL0 will output a low voltage, and the initial output terminal ZBL0 will output a high voltage, The first initial transistor 56 and the second initial transistor 58 are in a path state and an open state, respectively, further causing the first and second terminals Ν and ΖΝ to be low voltage and high voltage, respectively, and at the same time, due to the mode selection input terminal ZPGM is a low voltage, so that the comparison signal ZWL is a low voltage, and the first and second logic units cause their first transistor 52 to be turned on because of the low voltage input to the word line terminal, so that the second transistor is Electricity stored in the gate

Page 14 1281671 V. Description of the invention (ίο) The number of sub-charges will be changed according to the bit step of the first and second logic-independent voltages, into the 36 state and the elimination state (Erase stat power, The gate of the gate contains an electronic charge) (electron charge) and the gate of the data storage nt second transistor is not planted. By the same principle, V and the first logic unit 36, 38 two logical units 36, 38 will be divided; the second 'th and the first and the first material are stored in the first and second logical single it 36 38 ΐ 而 而 将

Program State, after the first Ί 3 8 is in the state of writing, and the process of testing the product, the plurality of selected fuse circuits have been swayed, and the memory is regarded as a qualified product. It will be installed in a certain ^, απ. When the electronic product of the memory is used to activate the power supply, the memory device for reading the plurality of selected fuse circuits is correctly selected, and then the memory unit is correctly selected. The letter ^ ^ I I replaces the function of the faulty memory unit, so that the word Ϊ ^ ^ is correctly operated. Here, one of the plurality of selections of melting money, such as one of the two, is used as an example, and the principle of the selection of the fuse circuit in the fourth embodiment of the fuse circuit is illustrated. P selects the silk circuit 30 for data reading when the 'mode selection input ☆ recognizes the "wheel input - high voltage (Vcc) (that is, represents the selection of the melting circuit 30, #, formula), then the initial output terminals BL0 and ZBL0 Both will output low-power Dushen. The first and second initial transistors 5 6 and 5 8 are in an open state. ° Figure 4 shows the signal value of Figure 4 as shown in Figure 6

Page 15

1281671 V. Invention Description (11) In this case, when the power is turned on, as shown in Figure 6, the power supply voltage V cc will increase with time until it reaches a preset value, and according to the action of selecting the fuse circuit 30 Can be divided into data sensing and data latching two stages. Please note that the information stored in the first and second logic units 3 6 and 38 must be inverted, that is, if the first logic unit 36 is in the write operation. The second logic unit 3 8 must be in the erase state, and the second logic unit 3 8 must be in the write state if the first logic unit 36 is in the erase state. When the fuse circuit 30 is selected to be in the data sensing phase, the voltage values of the first and second terminals N and ZN increase with the power supply voltage Vcc, since the value of the power supply voltage Vcc has not yet reached the first and the The voltage values of the two terminals N and ZN are different due to the different states of the first and second logic units 36 and 38, so the voltage values of the first and second terminals N and ZN are the same. The voltage, plus the mode selection input terminal ZPGM is a high voltage, then the function of the plurality of logic gates in the comparator 34 shown in FIG. 3 causes the comparison signal ZWL to be a low voltage to make the first and the first The first transistor 52 of the two logic cells 36, 38 maintains the path state, and thus the first and second terminals N, ZN will sense the data stored in the first and second logic cells 36, 38. When the fuse circuit 30 is selected to enter the data latching phase, since the value of the power supply voltage Vcc has reached such that the voltage values of the first and second terminals N, ZN are due to the first and second logic units 36, 38 The state of the difference is different, so the voltage values of the first and second endpoints N and ZN will be different, such as

Page 16 1281671 V. Description of the Invention (12) As shown in FIG. 6 (the case shown in FIG. 6 is when the first logic unit 36 is in the write state and the second logic unit 38 is in the cancel state), At this time, through the action of the plurality of logic gates in the comparator 34, the comparison signal ZWL will be converted to a high voltage as shown in FIG. 6, and the first transistors of the first and second logic units 36, 38 will be turned off. Therefore, the first and second endpoints N, ZN will stop the action of sensing the data and latch the data into the latch 32 according to the result of the sensing (as shown in FIG. 6, the first endpoint N) For the high voltage, the second terminal ZN is a low voltage), thus completing the reading action. In addition, the comparator 34 of the fuse circuit 30 further includes a signal output terminal Vout for outputting the latching signal of the latch 32. In this embodiment, the first terminal N is a high voltage. The signal output terminal V 〇ut outputs a low voltage through the function of the plurality of logic gates in the comparator 34, that is, the logic values are shown in FIG. 7 and FIG. 8. FIG. 7 shows another embodiment of the present invention. The schematic diagram of the fuse circuit 60 is selected. The fuse circuit 60 includes a latch 6 2, a comparator 64, a first logic unit 6 6 and a second logic unit 68, and the figure 8 shows A schematic diagram of a single programmable logic unit 70 used by the first and second logic units 6 6 and 6 8 of FIG. 7 , the single programmable logic unit 70 includes a first transistor 8 2 and a The second transistor 84, and the transistors 82, 84 are N-type metal oxide semiconductor transistors, wherein the connections between the various elements are very similar to the selection fuse circuit 30 and the single programmable logic unit 40. Therefore, there is no need to repeat the details. However, the interconnection of the plurality of logic gates in the comparator 64 is compared with the needs as needed.

Page 17 1281671 V. Inventive Description (13) The device 34 has the same 'and the comparator 64 outputs a comparison signal to the first and first logic units 66, 68, and a single programmable logic unit 70 The source of the first transistor 82 is electrically connected to a ground voltage Vss (〇v). The operation of selecting the fuse circuit 60 in the write mode and the read mode is also very similar to the selection of the fuse circuit 30, so that the same result is obtained in accordance with the above-described operation of the selected fuse circuit 30. In addition, the selection fuse circuit 60 in FIG. 7 also includes a first initial transistor 86 and a second initial 88, which are connected and operated in the same manner as the selection fuse circuit 30 of FIG. The initial transistors 5 6 and 5 8 are very similar, however, the first and the first, the transistors 86, 88 are all p-type metal oxide semiconductor transistors - the initial poles are electrically connected to - high voltage (here Vcc ). Compared with the conventional selection fuse circuit technology, the circuit of the present invention uses an latch, a comparator and two logic units=fuse in the write mode to set an initial value in the two logic units. In the mode, when the power is turned on, the latch is used to sense the data stored in the read element and outputted, thereby avoiding the reliability reduction caused by the conventional technology for the logic single-battering technology. And the test time has passed the use of the laser. Since the selected fuse circuit of the present invention is manufactured by using the standard complementary type and the semiconductor process technology, only a single layer of oxide layer is needed in the process, so that the conventional technology can also be avoided. The problem of using flash memory and two crystals. 9 Plus Manufacturing The above description is only a preferred embodiment of the present invention, and the present invention is applied for.

1281671 V. INSTRUCTIONS (14) Equivalent changes and modifications made to the scope of patents fall within the scope of the invention.

Page 19 1281671 BRIEF DESCRIPTION OF THE DRAWINGS BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a conventionally selected fuse circuit. Figure 2A is a schematic illustration of the layout of the selected fuse of Figure 1 when it has not been blown. FIG. 2B is a schematic view showing the layout of the selected fuse when it is blown. Figure 3 is a schematic illustration of a selected fuse circuit of the present invention. Figure 4 is a schematic diagram of one embodiment of the selection fuse circuit of Figure 3. Figure 5 is a schematic diagram of the logic unit of Figure 4. Figure 6 is a schematic diagram of the signal value of Figure 4 as a function of time. Figure 7 is a schematic diagram of another embodiment of the selection fuse circuit of Figure 3. Figure 8 is a schematic diagram of the logic unit of Figure 7. Symbols shown in the figure 10' 20^ 30' 60 selection fuse circuit 12^14, 42> 44 P-type metal oxide semiconductor transistor 16^46> 48 N-type metal oxide semiconductor transistor 18 Select fuse 11, 32^ 62 Latch 2 [ 34^ 64 Comparator 26^ 36^ 66 First Logic Unit 28^ 38^ 68 Second Logic Unit 40> 70 Single Programmable Logic Unit

Page 20 1281671 Brief description of the diagram 52^ 82 54^ 84 56^ 86 58^ 88 First transistor Second transistor First initial transistor Second initial transistor

Page 21

Claims (1)

1281671 VI. Patent Application Range 1. An Option Fuse Circuit, which is fabricated using the Standard CMOS Semiconductor Process (Standard CMOS Technology) process. The selection and dissolution circuit includes A latch includes a first end point and a second end point for latching signals of the first and second end points; a comparator (Comparator) including two inputs The first input terminal and the second end end are respectively electrically connected to the first and second end points, and the comparator is configured to input the signals of the first and second end points respectively on the two input ends, and compare the The second signal outputs a comparison signal at the output end; a first logic unit (Logic Cell) for storing a non-volatile data, the first logic unit includes a first word line (Word L i ne) end And a first bit line (Bit L i ne) end, the first word line end is electrically connected to the output end of the comparator to input the comparison signal, and the first bit line end is electrically connected To the first endpoint; a second logic unit for storing a non-volatile data, the second logic unit includes a second word line end and a second bit line end, the second word line end is electrically connected to the comparison The output end of the device inputs the comparison signal, and the second bit line end is electrically connected to the second end point; wherein the data stored in the first logic unit is related to the data system stored in the second logic unit Complementary. 2. Select the fuse circuit as described in item 1 of the patent application, which is in Read Mode and when the power is turned on, a power supply is supplied. Page 22 1281671 VI. Patent Application Range The pressure will increase with time until a preset value is reached. The voltage values of the first and second bit lines will increase with the power supply voltage. 3. If the selection fuse circuit described in claim 2 is applied, if the voltages of the first and second bit line terminals are equal to each other during the incrementing process, the comparison signal output by the comparator causes The first and second logic units are in a Turn-On state, and the first endpoint senses data stored by the first logic unit, and the second endpoint senses the second logic unit Information stored. 4. If the selection fuse circuit described in claim 2 is applied, if the voltages of the first and second bit line terminals are different from each other during the incrementing process, the comparison signal output by the comparator is The first and second logic units are in a Turn-Off state, and the flash lock flashes the signals of the first and second terminals. 5. The selective fuse circuit of claim 1, wherein the latch is formed by inverting the two inverters. 6. The selective fuse circuit according to claim 5, wherein the inverter is composed of a P-type metal oxide semiconductor transistor (PM0S Transistor) and an N-type metal oxide semiconductor transistor (NM0S T) a ransist 〇r), the gates of the two transistors are electrically connected to each other to be an input end of the inverter, and the drains of the two transistors are electrically connected to each other Page 23 1281671 VI. Patent Application Range One output of the inverter. 7. The selective fuse circuit of claim 1, wherein the comparator includes a plurality of logic gates (L 〇gic Gate) for comparing the signals of the first and second terminals. The output outputs the comparison signal. 8. The selection fuse circuit of claim 1, wherein the comparator further comprises a mode selection input for determining whether the selection fuse circuit is in a write mode or in a read mode. Take the mode. 9. The selective fuse circuit of claim 1, wherein the comparator further comprises a data write input for inputting the first fuse when the select fuse circuit is in the write mode Information on the second logical unit. The selection fuse circuit of claim 1, wherein the first and second logic units are One-Time Programmable Cell 〇1 1. The selected fuse circuit of claim 10, wherein the single programmable logic unit comprises a first transistor and a second transistor, the source of the first transistor being electrically connected to a power supply voltage a gate of the first transistor as a word line end of the logic unit, the first transistor Page 24 1281671 6. The bottom of the patent application range is electrically connected to the source of the second transistor, the gate of the second transistor is floating (F 1 〇ating), and the second transistor The pole is used as the bit line end of the logic unit. 1 2. The selective fuse circuit according to claim 11, wherein the first and second electro-crystalline systems are P-type metal oxide semiconductor transistors, and the source of the first transistor is electrically Connect to a high voltage. 1. The selective fuse circuit of claim 11, wherein the first and second electro-crystalline systems are N-type metal oxide semiconductor transistors, and the source of the first transistor is electrically connected To a ground voltage (0 V). The selection fuse circuit of claim 1, further comprising an initial module electrically connected to the first and second logic units for writing data to the write mode First and second logical units. The selective fuse circuit of claim 14, wherein the initial module comprises a first initial transistor and a second initial transistor, and the first and second initial crystal systems are An N-type metal oxide semiconductor transistor having a drain electrically connected to the first and second bit line ends, a source electrically connected to a ground voltage, and a comparator having a second phase opposite The initial output terminals are electrically connected to the gates of the first and second initial transistors, respectively, for controlling the conduction of the first and second initial transistors to write the data into the first and second logic units . </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The first and second initial electro-crystal system are P-type metal oxide semiconductor transistors, the drains of which are electrically connected to the first and second bit line ends, respectively, and the sources are electrically connected to a high voltage, and the source The comparator further includes an initial output terminal having two opposite phases, electrically connected to the gates of the first and second initial transistors, respectively, for controlling the conduction of the first and second initial transistors to write the data The first and second logical units are entered. The selection fuse circuit of claim 1, wherein the comparator further comprises a signal output for outputting the latch latch signal. Page 26