JP4170630B2 - ターミネーション回路のインピーダンスアップデート装置及び方法 - Google Patents

ターミネーション回路のインピーダンスアップデート装置及び方法 Download PDF

Info

Publication number
JP4170630B2
JP4170630B2 JP2002023516A JP2002023516A JP4170630B2 JP 4170630 B2 JP4170630 B2 JP 4170630B2 JP 2002023516 A JP2002023516 A JP 2002023516A JP 2002023516 A JP2002023516 A JP 2002023516A JP 4170630 B2 JP4170630 B2 JP 4170630B2
Authority
JP
Japan
Prior art keywords
impedance
update
terminator
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002023516A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002330182A (ja
JP2002330182A5 (enExample
Inventor
金南錫
趙郁來
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2002330182A publication Critical patent/JP2002330182A/ja
Publication of JP2002330182A5 publication Critical patent/JP2002330182A5/ja
Application granted granted Critical
Publication of JP4170630B2 publication Critical patent/JP4170630B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/40Impedance converters
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0298Arrangement for terminating transmission lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2002023516A 2001-02-05 2002-01-31 ターミネーション回路のインピーダンスアップデート装置及び方法 Expired - Fee Related JP4170630B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2001-0005340A KR100410536B1 (ko) 2001-02-05 2001-02-05 터미네이션 회로의 임피던스 업데이트 장치 및 방법
KR2001-005340 2001-02-05

Publications (3)

Publication Number Publication Date
JP2002330182A JP2002330182A (ja) 2002-11-15
JP2002330182A5 JP2002330182A5 (enExample) 2005-07-28
JP4170630B2 true JP4170630B2 (ja) 2008-10-22

Family

ID=19705327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002023516A Expired - Fee Related JP4170630B2 (ja) 2001-02-05 2002-01-31 ターミネーション回路のインピーダンスアップデート装置及び方法

Country Status (5)

Country Link
US (1) US6556038B2 (enExample)
JP (1) JP4170630B2 (enExample)
KR (1) KR100410536B1 (enExample)
DE (1) DE10151745B4 (enExample)
TW (1) TWI278182B (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864706B1 (en) * 2000-07-20 2005-03-08 Silicon Graphics, Inc. GTL+Driver
US7356555B2 (en) * 2002-03-29 2008-04-08 Intel Corporation In-protocol impedance compensation control
US6968413B2 (en) * 2002-10-07 2005-11-22 International Business Machines Corporation Method and system for configuring terminators in a serial communication system
US7239170B2 (en) * 2003-07-08 2007-07-03 Lsi Corporation Apparatus and methods for improved input/output cells
US6930507B2 (en) * 2003-07-10 2005-08-16 International Business Machines Corporation Thevenins receiver
US6912165B2 (en) * 2003-08-22 2005-06-28 International Business Machines Corporation Method for transparent updates of output driver impedance
US7057415B2 (en) * 2003-12-10 2006-06-06 Hewlett-Packard Development Company, L.P. Output buffer compensation control
TWI304529B (en) * 2004-01-30 2008-12-21 Realtek Semiconductor Corp Impedance control circuit and method thereof
KR100604851B1 (ko) * 2004-04-06 2006-07-31 삼성전자주식회사 선택적으로 입출력 신호의 스윙 폭을 변경시키는 고속출력 회로, 고속 입력 회로, 및 입출력 신호의 스윙 폭변경방법
US7102381B2 (en) * 2004-06-29 2006-09-05 Intel Corporation Adaptive termination for optimum signal detection
JP4143615B2 (ja) 2005-03-03 2008-09-03 エルピーダメモリ株式会社 オンダイターミネーション回路
US7327167B2 (en) * 2005-04-28 2008-02-05 Silicon Graphics, Inc. Anticipatory programmable interface pre-driver
KR100702838B1 (ko) * 2005-05-09 2007-04-03 삼성전자주식회사 반도체 장치에서의 임피던스 콘트롤러블 출력 구동회로 및그에 따른 임피던스 콘트롤 방법
KR100684904B1 (ko) * 2005-08-05 2007-02-20 삼성전자주식회사 온 다이 종단 회로를 포함한 반도체 메모리 장치 및 그것의온 다이 종단 방법
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치
KR100780657B1 (ko) * 2006-09-27 2007-11-30 주식회사 하이닉스반도체 반도체메모리소자 및 그의 구동 방법
JP4876987B2 (ja) * 2007-03-12 2012-02-15 住友電気工業株式会社 受信回路
US10608634B2 (en) * 2007-06-08 2020-03-31 Conversant Intellectual Property Management Inc. Dynamic impedance control for input/output buffers
TW200921595A (en) * 2007-11-14 2009-05-16 Darfon Electronics Corp Multi-lamp backlight apparatus
US7915912B2 (en) * 2008-09-24 2011-03-29 Rambus Inc. Signal lines with internal and external termination
KR101086884B1 (ko) * 2010-09-30 2011-11-25 주식회사 하이닉스반도체 임피던스 제어신호 발생 회로 및 반도체 회로의 임피던스 제어 방법
KR101004285B1 (ko) * 2010-10-05 2011-01-03 (주)한동알앤씨 버스 승강장에 설치된 태양광 조명 시스템
JP5757888B2 (ja) * 2012-01-17 2015-08-05 ルネサスエレクトロニクス株式会社 半導体装置
KR102717627B1 (ko) * 2016-12-26 2024-10-16 에스케이하이닉스 주식회사 동적 터미네이션 회로, 이를 포함하는 반도체 장치 및 시스템
JP6859945B2 (ja) * 2017-12-25 2021-04-14 株式会社デンソー リンギング抑制回路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134311A (en) * 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
JPH06125261A (ja) * 1992-10-13 1994-05-06 Mitsubishi Electric Corp 入力回路
JPH06291639A (ja) * 1993-03-19 1994-10-18 Hewlett Packard Co <Hp> 集積回路における信号線終端装置
JPH07245543A (ja) * 1994-03-02 1995-09-19 Nec Corp バスシステム
JP2897672B2 (ja) * 1995-01-13 1999-05-31 日本電気株式会社 信号伝送回路
DE19639230C1 (de) * 1996-09-24 1998-07-16 Ericsson Telefon Ab L M Ausgangspufferschaltkreis zur Ansteuerung einer Übertragungsleitung
US5955894A (en) * 1997-06-25 1999-09-21 Sun Microsystems, Inc. Method for controlling the impedance of a driver circuit
JPH1127132A (ja) * 1997-07-01 1999-01-29 Hitachi Ltd インピーダンスマッチング回路および半導体記憶装置
US6127840A (en) * 1998-03-17 2000-10-03 International Business Machines Corporation Dynamic line termination clamping circuit
US6118310A (en) * 1998-11-04 2000-09-12 Agilent Technologies Digitally controlled output driver and method for impedance matching
JP2001024497A (ja) * 1999-07-06 2001-01-26 Hitachi Ltd 自己整合式ディジタルドライバ回路

Also Published As

Publication number Publication date
KR100410536B1 (ko) 2003-12-18
JP2002330182A (ja) 2002-11-15
DE10151745A1 (de) 2002-08-29
TWI278182B (en) 2007-04-01
KR20020065021A (ko) 2002-08-13
DE10151745B4 (de) 2006-02-09
US6556038B2 (en) 2003-04-29
US20020118037A1 (en) 2002-08-29

Similar Documents

Publication Publication Date Title
JP4170630B2 (ja) ターミネーション回路のインピーダンスアップデート装置及び方法
US6175928B1 (en) Reducing timing variance of signals from an electronic device
US6320406B1 (en) Methods and apparatus for a terminated fail-safe circuit
US20080303558A1 (en) Data output driver circuit
US7268602B2 (en) Method and apparatus for accommodating delay variations among multiple signals
JP3795685B2 (ja) トライステート感知回路とこれを備える信号発生回路
EP1332593B1 (en) Pre-emphasis scheme
JP4841786B2 (ja) 低待ち時間多重レベル通信インタフェース
US5751161A (en) Update scheme for impedance controlled I/O buffers
KR100391150B1 (ko) 다단의 상위 코드 선택기를 갖는 반도체 장치의 임피던스콘트롤 출력회로 및 그의 동작방법
US7259592B2 (en) Output drivers having adjustable swing widths during test mode operation
KR20050022836A (ko) 반도체 장치의 온 다이 터미네이션 회로 및 방법
US20020133650A1 (en) Boundary scannable one bit precompensated cmos driver with compensating pulse width control
US6801054B2 (en) Output buffer circuit
US5942918A (en) Method for resolving differential signals
EP1760889A2 (en) High speed input circuit
KR20010006870A (ko) 버퍼 임계치의 동적 스위칭을 위한 회로
US8248129B2 (en) Signal delay circuit, clock transfer control circuit and semiconductor device having the same
US8248103B2 (en) Output circuit of semiconductor device
KR100455736B1 (ko) 프리세트기능을 갖는 출력버퍼회로_
JP4086193B2 (ja) オープンドレイン出力バッファ
JP3206737B2 (ja) ラッチ回路
US12489444B2 (en) Receiver circuit including differential buffer
KR100508722B1 (ko) 펄스폭 고정 장치
JP2009284427A (ja) 半導体装置及び半導体装置の制御方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041217

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041217

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061222

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20070319

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20070323

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071130

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080124

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080129

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20080201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080530

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080613

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080708

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080807

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4170630

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120815

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120815

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130815

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees