JP4001866B2 - 浅溝分離(sti)プロセス後のディボット形成を制限する方法 - Google Patents
浅溝分離(sti)プロセス後のディボット形成を制限する方法 Download PDFInfo
- Publication number
- JP4001866B2 JP4001866B2 JP2003546380A JP2003546380A JP4001866B2 JP 4001866 B2 JP4001866 B2 JP 4001866B2 JP 2003546380 A JP2003546380 A JP 2003546380A JP 2003546380 A JP2003546380 A JP 2003546380A JP 4001866 B2 JP4001866 B2 JP 4001866B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide
- oxide layer
- layer
- sti
- thermal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 52
- 230000015572 biosynthetic process Effects 0.000 title claims description 23
- 238000002955 isolation Methods 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 53
- 229910052710 silicon Inorganic materials 0.000 claims description 53
- 239000010703 silicon Substances 0.000 claims description 53
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 3
- 238000003795 desorption Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 230000003139 buffering effect Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-O azanium;hydrofluoride Chemical compound [NH4+].F LDDQLRUQCUTJBB-UHFFFAOYSA-O 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (8)
- 浅溝分離(STI)構造のディボットの形成を制限する方法であって、順に、 シリコン領域(260)に形成されたトレンチ(285)内に、高密度プラズマ(HDP)酸化物(290)を設けるステップと、 前記シリコン領域(260)の上層を酸化して前記シリコン領域(260)の上面に熱酸化物層(302)を形成するステップと、 前記熱酸化物層(302)および前記高密度プラズマ酸化物(290)に窒素を注入するステップと、 化学的酸化物除去(COR)プロセスを用いて前記熱酸化物(302)を前記高密度プラズマ酸化物(290)に対して選択的にエッチングするステップとを含み、前記熱酸化物が前記高密度プラズマ酸化物(290)よりも速くエッチングされる方法。
- 浅溝分離(STI)構造を形成する方法であって、 シリコン領域(260)上に第1の熱酸化物層(270)を形成するステップと、 前記第1の熱酸化物層(270)を通して前記シリコン領域(260)にトレンチ(285)を形成するステップと、 前記トレンチ(285)内に、高密度プラズマ(HDP)酸化物(290)を設けるステップと、 前記第1の熱酸化物層(270)および前記高密度プラズマ酸化物(290)の上面部分を除去するステップと、 前記シリコン領域(260)上に第2の熱酸化物層(302)を形成するステップと、 前記第2の熱酸化物層(302)および前記高密度プラズマ酸化物(290)に窒素を注入するステップと、 化学的酸化物除去(COR)プロセスを用いて前記第2の熱酸化物層(302)の予め定められた部分を前記高密度プラズマ酸化物(290)に対して選択的にエッチングするステップとを含み、前記第2の熱酸化物層(302)が、前記高密度プラズマ酸化物(290)よりも速くエッチングされる方法。
- 前記選択エッチングが、前記トレンチ(285)の周囲に沿ってディボット(305)を形成しないか、またはディボット(305)の最大直線寸法(D8、D9)が500Åを超えないように前記トレンチ(285)の周囲に沿って前記ディボット(305)を形成する、請求項1または2に記載の方法。
- 熱酸化物(302)と高密度プラズマ酸化物(290)のエッチング速度比が少なくとも2:1である、請求項1に記載の方法。
- 前記化学的酸化物除去プロセスが、少なくとも一連のNH3とHFの混合物を使用する蒸気エッチング・ステップとそれに続く脱着アニール・ステップとを含む、請求項1または2に記載の方法。
- 前記第1の熱酸化物層(270)および前記高密度プラズマ酸化物(290)の上面部分を除去する前記ステップが、希釈HFエッチング、緩衝HFエッチング、および化学的な酸化物除去から成るグループから選択されたプロセスを使用して行われる、請求項2に記載の方法。
- さらに、前記第1の熱酸化物層(270)の前記除去の後で、前記シリコン領域(260)の上に第3の熱酸化物層(300)を形成するステップと、 前記第3の熱酸化物層(300)、および前記高密度プラズマ酸化物(290)の他の上面部分を除去するステップとを含み、 前記第3の熱酸化物層を除去する前記ステップが、希釈HFエッチング、緩衝HFエッチング、および化学的な酸化物除去から成るグループから選択される、請求項2に記載の方法。
- 前記第2の熱酸化物層(302)の高密度プラズマ酸化物(290)に対するエッチング速度比が少なくとも2:1である、請求項2に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/989,585 US6541351B1 (en) | 2001-11-20 | 2001-11-20 | Method for limiting divot formation in post shallow trench isolation processes |
PCT/US2002/036397 WO2003044833A2 (en) | 2001-11-20 | 2002-11-14 | Method for limiting divot formation in post shallow trench isolation processes |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005510080A JP2005510080A (ja) | 2005-04-14 |
JP4001866B2 true JP4001866B2 (ja) | 2007-10-31 |
Family
ID=25535245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003546380A Expired - Fee Related JP4001866B2 (ja) | 2001-11-20 | 2002-11-14 | 浅溝分離(sti)プロセス後のディボット形成を制限する方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6541351B1 (ja) |
EP (1) | EP1464074B1 (ja) |
JP (1) | JP4001866B2 (ja) |
KR (1) | KR100560578B1 (ja) |
CN (1) | CN1613141A (ja) |
AU (1) | AU2002357717A1 (ja) |
TW (1) | TWI220063B (ja) |
WO (1) | WO2003044833A2 (ja) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072063A (ja) * | 2002-06-10 | 2004-03-04 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6713385B1 (en) * | 2002-10-31 | 2004-03-30 | Intel Corporation | Implanting ions in shallow trench isolation structures |
US6905941B2 (en) * | 2003-06-02 | 2005-06-14 | International Business Machines Corporation | Structure and method to fabricate ultra-thin Si channel devices |
US20050227494A1 (en) * | 2004-03-30 | 2005-10-13 | Tokyo Electron Limited | Processing system and method for treating a substrate |
US6852584B1 (en) * | 2004-01-14 | 2005-02-08 | Tokyo Electron Limited | Method of trimming a gate electrode structure |
US7094127B2 (en) * | 2004-03-01 | 2006-08-22 | Milliken & Company | Apparel articles including white polyurethane foams that exhibit a reduction in propensity for discoloring |
US7097779B2 (en) * | 2004-07-06 | 2006-08-29 | Tokyo Electron Limited | Processing system and method for chemically treating a TERA layer |
KR100539275B1 (ko) * | 2004-07-12 | 2005-12-27 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
CN100449709C (zh) * | 2005-02-14 | 2009-01-07 | 东京毅力科创株式会社 | 基板处理方法、清洗方法、电子设备的制造方法和程序 |
JP4843285B2 (ja) * | 2005-02-14 | 2011-12-21 | 東京エレクトロン株式会社 | 電子デバイスの製造方法及びプログラム |
US7510972B2 (en) * | 2005-02-14 | 2009-03-31 | Tokyo Electron Limited | Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device |
JP4933763B2 (ja) | 2005-02-18 | 2012-05-16 | 東京エレクトロン株式会社 | 固体撮像素子の製造方法、薄膜デバイスの製造方法及びプログラム |
US8802537B1 (en) * | 2005-07-27 | 2014-08-12 | Spansion Llc | System and method for improving reliability in a semiconductor device |
DE102005037566B4 (de) * | 2005-08-09 | 2008-04-24 | Qimonda Ag | Herstellungsverfahren für eine Halbleiterstruktur und entsprechende Halbleiterstruktur |
JP5119604B2 (ja) * | 2006-03-16 | 2013-01-16 | ソニー株式会社 | 半導体装置の製造方法 |
US7795148B2 (en) * | 2006-03-28 | 2010-09-14 | Tokyo Electron Limited | Method for removing damaged dielectric material |
US7446007B2 (en) * | 2006-11-17 | 2008-11-04 | International Business Machines Corporation | Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof |
US20090053834A1 (en) * | 2007-08-23 | 2009-02-26 | Vladimir Alexeevich Ukraintsev | Use of scatterometry for in-line detection of poly-si strings left in sti divot after gate etch |
JP5374039B2 (ja) * | 2007-12-27 | 2013-12-25 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置及び記憶媒体 |
CN101958268B (zh) * | 2009-07-21 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | 隔离结构的制作方法 |
US9953885B2 (en) | 2009-10-27 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI shape near fin bottom of Si fin in bulk FinFET |
US8110466B2 (en) | 2009-10-27 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cross OD FinFET patterning |
US9130058B2 (en) | 2010-07-26 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
CN102412182B (zh) * | 2010-09-19 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽隔离结构形成方法 |
CN102569161B (zh) * | 2010-12-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | 半导体器件制造方法 |
CN102543672A (zh) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | 去除自然氧化硅层和形成自对准硅化物的方法 |
CN102569083B (zh) * | 2010-12-23 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 具有高k金属栅极的金属氧化物半导体的形成方法 |
US8735972B2 (en) | 2011-09-08 | 2014-05-27 | International Business Machines Corporation | SRAM cell having recessed storage node connections and method of fabricating same |
CN103151295B (zh) * | 2011-12-07 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US8603895B1 (en) | 2012-09-11 | 2013-12-10 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence |
KR102277398B1 (ko) * | 2014-09-17 | 2021-07-16 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
JP2017152531A (ja) * | 2016-02-24 | 2017-08-31 | 東京エレクトロン株式会社 | 基板処理方法 |
JP6977474B2 (ja) * | 2017-10-23 | 2021-12-08 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US10510855B2 (en) * | 2017-11-14 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor layout to reduce kink effect |
DE102018114750A1 (de) | 2017-11-14 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor-layout zum reduzieren des kink-effekts |
US10468410B2 (en) * | 2017-11-15 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate modulation to improve kink effect |
KR102564326B1 (ko) | 2018-10-29 | 2023-08-08 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US11239313B2 (en) | 2018-10-30 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip and method of forming thereof |
US11127621B2 (en) * | 2019-11-04 | 2021-09-21 | United Microelectronics Corp. | Method of forming semiconductor device |
TWI744004B (zh) * | 2020-09-23 | 2021-10-21 | 力晶積成電子製造股份有限公司 | 減少淺溝渠隔離結構邊緣凹陷的方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5282925A (en) * | 1992-11-09 | 1994-02-01 | International Business Machines Corporation | Device and method for accurate etching and removal of thin film |
US5316965A (en) * | 1993-07-29 | 1994-05-31 | Digital Equipment Corporation | Method of decreasing the field oxide etch rate in isolation technology |
US5447884A (en) * | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5923991A (en) * | 1996-11-05 | 1999-07-13 | International Business Machines Corporation | Methods to prevent divot formation in shallow trench isolation areas |
US6165853A (en) * | 1997-06-16 | 2000-12-26 | Micron Technology, Inc. | Trench isolation method |
US5960297A (en) | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US6051478A (en) * | 1997-12-18 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of enhancing trench edge oxide quality |
TW379405B (en) | 1998-02-13 | 2000-01-11 | United Integrated Circuits Corp | Manufacturing method of shallow trench isolation structure |
KR100280107B1 (ko) | 1998-05-07 | 2001-03-02 | 윤종용 | 트렌치 격리 형성 방법 |
KR100275730B1 (ko) | 1998-05-11 | 2000-12-15 | 윤종용 | 트렌치 소자분리 방법 |
US6093619A (en) | 1998-06-18 | 2000-07-25 | Taiwan Semiconductor Manufaturing Company | Method to form trench-free buried contact in process with STI technology |
KR100292616B1 (ko) | 1998-10-09 | 2001-07-12 | 윤종용 | 트렌치격리의제조방법 |
US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
TW410423B (en) | 1998-10-21 | 2000-11-01 | United Microelectronics Corp | Manufacture method of shallow trench isolation |
US20010014513A1 (en) | 1999-01-20 | 2001-08-16 | Max G. Levy | Sti divot and seam elimination |
US6027982A (en) | 1999-02-05 | 2000-02-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures with improved isolation fill and surface planarity |
US6248641B1 (en) | 1999-02-05 | 2001-06-19 | United Microelectronics Corp. | Method of fabricating shallow trench isolation |
TW530372B (en) * | 1999-03-09 | 2003-05-01 | Mosel Vitelic Inc | Shallow trench isolation process |
US6165871A (en) | 1999-07-16 | 2000-12-26 | Chartered Semiconductor Manufacturing Ltd. | Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device |
TW432594B (en) * | 1999-07-31 | 2001-05-01 | Taiwan Semiconductor Mfg | Manufacturing method for shallow trench isolation |
US6245619B1 (en) * | 2000-01-21 | 2001-06-12 | International Business Machines Corporation | Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devices |
US6271094B1 (en) * | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
US6335261B1 (en) * | 2000-05-31 | 2002-01-01 | International Business Machines Corporation | Directional CVD process with optimized etchback |
-
2001
- 2001-11-20 US US09/989,585 patent/US6541351B1/en not_active Expired - Lifetime
-
2002
- 2002-10-22 TW TW091124420A patent/TWI220063B/zh not_active IP Right Cessation
- 2002-11-14 AU AU2002357717A patent/AU2002357717A1/en not_active Abandoned
- 2002-11-14 KR KR1020047001393A patent/KR100560578B1/ko not_active IP Right Cessation
- 2002-11-14 WO PCT/US2002/036397 patent/WO2003044833A2/en active Application Filing
- 2002-11-14 CN CNA028204107A patent/CN1613141A/zh active Pending
- 2002-11-14 JP JP2003546380A patent/JP4001866B2/ja not_active Expired - Fee Related
- 2002-11-14 EP EP02792254.1A patent/EP1464074B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
TWI220063B (en) | 2004-08-01 |
WO2003044833A3 (en) | 2003-11-27 |
JP2005510080A (ja) | 2005-04-14 |
CN1613141A (zh) | 2005-05-04 |
EP1464074A4 (en) | 2009-06-03 |
EP1464074B1 (en) | 2013-07-17 |
AU2002357717A1 (en) | 2003-06-10 |
WO2003044833A2 (en) | 2003-05-30 |
US6541351B1 (en) | 2003-04-01 |
EP1464074A2 (en) | 2004-10-06 |
KR100560578B1 (ko) | 2006-03-14 |
AU2002357717A8 (en) | 2003-06-10 |
KR20040103896A (ko) | 2004-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4001866B2 (ja) | 浅溝分離(sti)プロセス後のディボット形成を制限する方法 | |
KR100316221B1 (ko) | 얕은트렌치격리신기술 | |
US7196396B2 (en) | Semiconductor device having STI without divot and its manufacture | |
US6245619B1 (en) | Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devices | |
JP4347431B2 (ja) | トレンチ素子分離方法 | |
US7611950B2 (en) | Method for forming shallow trench isolation in semiconductor device | |
JP3880466B2 (ja) | 薄いシリコン・オン・インシュレータ基板用の浅いトレンチ分離を形成する方法 | |
US8163625B2 (en) | Method for fabricating an isolation structure | |
US6642536B1 (en) | Hybrid silicon on insulator/bulk strained silicon technology | |
US6979867B2 (en) | SOI chip with mesa isolation and recess resistant regions | |
JPH11145273A (ja) | 半導体装置の製造方法 | |
US6271147B1 (en) | Methods of forming trench isolation regions using spin-on material | |
US6784075B2 (en) | Method of forming shallow trench isolation with silicon oxynitride barrier film | |
TW200421525A (en) | Method of forming shallow trench isolation(STI) with chamfered corner | |
US20130122684A1 (en) | Semiconductor process for removing oxide layer | |
KR100839894B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US6344374B1 (en) | Method of fabricating insulators for isolating electronic devices | |
JP2005353892A (ja) | 半導体基板、半導体装置及びその製造方法 | |
US6720235B2 (en) | Method of forming shallow trench isolation in a semiconductor substrate | |
US20030181014A1 (en) | Method of manufacturing semiconductor device with STI | |
US6900112B2 (en) | Process for forming shallow trench isolation region with corner protection layer | |
KR100200751B1 (ko) | 반도체장치의 소자분리방법 | |
JP2005072358A (ja) | 半導体装置の製造方法 | |
JP2000200830A (ja) | トレンチ素子分離領域を有する半導体装置の製造方法 | |
JP2003100868A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060612 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060926 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061220 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070814 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070815 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100824 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100824 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110824 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120824 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130824 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |