JP3953461B2 - 集積回路メモリ - Google Patents
集積回路メモリ Download PDFInfo
- Publication number
- JP3953461B2 JP3953461B2 JP2003509461A JP2003509461A JP3953461B2 JP 3953461 B2 JP3953461 B2 JP 3953461B2 JP 2003509461 A JP2003509461 A JP 2003509461A JP 2003509461 A JP2003509461 A JP 2003509461A JP 3953461 B2 JP3953461 B2 JP 3953461B2
- Authority
- JP
- Japan
- Prior art keywords
- bit
- write
- line
- bit line
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000003213 activating effect Effects 0.000 claims 2
- 235000014676 Phragmites communis Nutrition 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 230000000295 complement effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
11 微小電圧信号
12 ビット線電圧
14 基準ビット線電圧
16 SETP信号
18 メモリ・セル電圧
20 基準ビット線電圧
21 微小電位差
22 ビット線電圧
24 メモリ・セル電圧
50 群
51 センス・アンプ
52 センス・アンプ
53 センス・アンプ
54 センス・アンプ
56 制御ブロック
60 リード・バッファ
70 NANDゲート
72 NANDゲート
74 T3トランジスタ
76 T3トランジスタ
78 プリチャージ・デバイス
80 交差結合デバイス
90 微小電位差
92 微小電位差
BT 真のビット線
BC 基準ビット線
FT 真ファン・ノード
FC 相補ファン・ノード
T1 ビットスイッチ
T3 制御スイッチ
Claims (4)
- DRAM装置であって、
センス・アンプ、前記センス・アンプに接続された真のビット線及び基準ビット線、
メモリ・セルに格納されたデータを読み出すための読み出し(READ)線、
1を書き込むときに活性化される第1のライト(WRITE1N)線、
0を書き込むときに活性化される第2のライト(WRITE0N)線、
前記基準ビット線上に備えられ、メモリ・セルを選択する信号(BXP)により導通状態にされる第1のビットスイッチ(T1)、
前記真のビット線上に備えられ、メモリ・セルを選択する前記信号(BXP)により導通状態にされる第2のビットスイッチ(T1)、
前記基準ビット線上に、前記第1のビットスイッチ(T1)の下流に前記第1のビットスイッチ(T1)と直列に備えられ、プリチャージ制御信号(EQN)又は前記第1のライト(WRITE1N)線が活性化されることにより導通状態にされる第1のライト制御スイッチ(T3)、
前記真のビット線上に、前記第2のビットスイッチ(T1)の下流に前記第2のビットスイッチ(T1)と直列に備えられ、前記プリチャージ制御信号(EQN)又は前記第2のライト(WRITE0N)線が活性化されることにより導通状態にされる第2のライト制御スイッチ(T3)、
を備え、
書き込みの際には、
(1)メモリ・セルを選択する前記信号(BXP)により前記第1のビットスイッチ(T1)及び前記第2のビットスイッチ(T1)が導通状態にされ、
(2)1を書き込む際には、前記第1のライト(WRITE1N)線が活性化されて前記第1のライト制御スイッチ(T3)が導通状態にされ、前記基準ビット線が接地され、
(3)0を書き込む際には、前記第2のライト(WRITE0N)線が活性化されて前記第2のライト制御スイッチ(T3)が導通状態にされ、前記真のビット線が接地され、これにより向上された書き込み速度を示し、
プリチャージの際には、
前記プリチャージ制御信号(EQN)が活性化されて、前記第1のライト制御スイッチ(T3)及び前記第2のライト制御スイッチ(T3)が導通状態にされ、前記基準ビット線及び前記真のビット線が接地される、
ことを特徴とするDRAM装置。 - 前記基準ビット線上に、前記第1のビットスイッチ(T1)の下流に前記第1のビットスイッチ(T1)と直列に且つ前記第1のライト制御スイッチ(T3)と並列に備えられ、前記READ線を活性化することによって導通状態にされる第1のリード制御スイッチ(T2)、
前記真のビット線上に、前記第2のビットスイッチ(T1)の下流に前記第2のビットスイッチ(T1)と直列に且つ前記第2のライト制御スイッチ(T3)と並列に備えられ、前記READ線を活性化することによって導通状態にされる第2のリード制御スイッチ(T2)、
をさらに備え、
読み取りの際には、
(1)メモリ・セルを選択する前記信号(BXP)により前記第1のビットスイッチ(T1)及び前記第2のビットスイッチ(T1)が導通状態にされ、
(2)前記READ線が活性化されて、前記第1及び第2のリード制御スイッチが導通状態となって、夫々、前記基準ビット線及び前記真のビット線の電位をリード・バッファへ転送することを特徴とする請求項1記載のDRAM装置。 - 2組の基準ビット線及び真のビット線が、夫々の組の第1及び第2のビットスイッチ(T1)の下流で、基準ビット線同士及び真のビット線同士で電気的に接続された中間ファンノード(FC0 1 、FT0 1 )を有し、前記2組の基準ビット線が第1のリー ド制御スイッチ(T2)と第1のライト制御スイッチ(T3)を、前記2組の真のビット線が第2のリード制御スイッチ(T2)と第2のライト制御スイッチ(T3)を、夫々共用していることを特徴とする請求項1または2記載のDRAM装置。
- 第1のNANDゲート及び第2のNANDゲートをさらに備え、
第1のNANDゲートは、プリチャージ制御信号(EQN)及び前記第1のライト(WRITE1N)線上の信号を入力とし、前記第1のライト制御スイッチ(T3)に出力し、
第2のNANDゲートは、プリチャージ制御信号(EQN)及び前記第2のライト(WRITE0N)線上の信号を入力とし、前記第2のライト制御スイッチ(T3)に出力する、
請求項1〜3のいずれか1項記載のDRAM装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/896,746 US6400629B1 (en) | 2001-06-29 | 2001-06-29 | System and method for early write to memory by holding bitline at fixed potential |
PCT/US2001/047677 WO2003003376A1 (en) | 2001-06-29 | 2001-12-10 | System and method for early write to memory by holding bitline at fixed potential |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004531019A JP2004531019A (ja) | 2004-10-07 |
JP3953461B2 true JP3953461B2 (ja) | 2007-08-08 |
Family
ID=25406754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003509461A Expired - Fee Related JP3953461B2 (ja) | 2001-06-29 | 2001-12-10 | 集積回路メモリ |
Country Status (9)
Country | Link |
---|---|
US (1) | US6400629B1 (ja) |
EP (1) | EP1433179B1 (ja) |
JP (1) | JP3953461B2 (ja) |
KR (1) | KR100613317B1 (ja) |
CN (1) | CN100345213C (ja) |
AT (1) | ATE327555T1 (ja) |
DE (1) | DE60119995T2 (ja) |
TW (1) | TW574708B (ja) |
WO (1) | WO2003003376A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6788591B1 (en) | 2003-08-26 | 2004-09-07 | International Business Machines Corporation | System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch |
KR100590855B1 (ko) * | 2003-10-14 | 2006-06-19 | 주식회사 하이닉스반도체 | 전류 소모의 감소를 위한 반도체 메모리 소자 |
US7009905B2 (en) * | 2003-12-23 | 2006-03-07 | International Business Machines Corporation | Method and apparatus to reduce bias temperature instability (BTI) effects |
US7079427B2 (en) * | 2004-07-02 | 2006-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for a high-speed access architecture for semiconductor memory |
US7221605B2 (en) * | 2004-08-31 | 2007-05-22 | Micron Technology, Inc. | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets |
US7236415B2 (en) * | 2004-09-01 | 2007-06-26 | Micron Technology, Inc. | Sample and hold memory sense amplifier |
KR100720260B1 (ko) * | 2004-11-15 | 2007-05-22 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 로컬 입출력 라인 프리차지 회로 |
KR20090119143A (ko) * | 2008-05-15 | 2009-11-19 | 삼성전자주식회사 | 비트라인 센스 앰프, 이를 포함하는 메모리 코어 및 반도체메모리 장치 |
CN101359509B (zh) * | 2008-09-02 | 2010-06-02 | 北京芯技佳易微电子科技有限公司 | 一次性可编程存储器电路及其编程和读取方法 |
KR20110036211A (ko) * | 2009-10-01 | 2011-04-07 | 삼성전자주식회사 | 프리 센싱 및 분리 회로를 포함하는 반도체 메모리 장치 |
KR102048255B1 (ko) | 2012-10-25 | 2019-11-25 | 삼성전자주식회사 | 비트 라인 감지 증폭기 및 이를 포함하는 반도체 메모리 장치 및 메모리 시스템 |
GB2512844B (en) * | 2013-04-08 | 2017-06-21 | Surecore Ltd | Reduced Power Memory Unit |
US9281043B1 (en) * | 2014-12-24 | 2016-03-08 | Intel Corporation | Resistive memory write circuitry with bit line drive strength based on storage cell line resistance |
US11068639B2 (en) * | 2018-10-19 | 2021-07-20 | Arm Limited | Metal layout techniques |
JP2021034090A (ja) * | 2019-08-28 | 2021-03-01 | キオクシア株式会社 | 不揮発性半導体記憶装置 |
CN111863051B (zh) * | 2020-07-27 | 2022-11-22 | 安徽大学 | 灵敏放大器、存储器和灵敏放大器的控制方法 |
US11929112B2 (en) | 2020-07-27 | 2024-03-12 | Anhui University | Sense amplifier, memory, and method for controlling sense amplifier |
US11404127B1 (en) * | 2021-02-11 | 2022-08-02 | Sandisk Technologies Llc | Read refresh to improve power on data retention for a non-volatile memory |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS615495A (ja) | 1984-05-31 | 1986-01-11 | Toshiba Corp | 半導体記憶装置 |
US5007022A (en) | 1987-12-21 | 1991-04-09 | Texas Instruments Incorporated | Two-port two-transistor DRAM |
JP3101298B2 (ja) * | 1990-03-30 | 2000-10-23 | 株式会社東芝 | 半導体メモリ装置 |
US5237533A (en) * | 1991-12-20 | 1993-08-17 | National Semiconductor Corporation | High speed switched sense amplifier |
US5339274A (en) * | 1992-10-30 | 1994-08-16 | International Business Machines Corporation | Variable bitline precharge voltage sensing technique for DRAM structures |
DE69333909T2 (de) * | 1992-11-12 | 2006-07-20 | Promos Technologies, Inc. | Leseverstärker mit lokalen Schreibtreibern |
JPH07211068A (ja) | 1994-01-18 | 1995-08-11 | Matsushita Electric Ind Co Ltd | メモリ装置 |
US5677865A (en) * | 1995-09-11 | 1997-10-14 | Micron Technology, Inc. | Ferroelectric memory using reference charge circuit |
JPH09162305A (ja) * | 1995-12-08 | 1997-06-20 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH10111828A (ja) | 1996-09-27 | 1998-04-28 | Internatl Business Mach Corp <Ibm> | メモリシステム、データ転送方法 |
US5923593A (en) | 1996-12-17 | 1999-07-13 | Monolithic Systems, Inc. | Multi-port DRAM cell and memory system using same |
JPH1186539A (ja) | 1997-09-04 | 1999-03-30 | Canon Inc | データ処理装置、及び方法 |
JP2978871B2 (ja) | 1998-01-30 | 1999-11-15 | 日本電気アイシーマイコンシステム株式会社 | リフレッシュ制御方式 |
US5963497A (en) | 1998-05-18 | 1999-10-05 | Silicon Aquarius, Inc. | Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same |
-
2001
- 2001-06-29 US US09/896,746 patent/US6400629B1/en not_active Expired - Lifetime
- 2001-12-10 AT AT01995491T patent/ATE327555T1/de not_active IP Right Cessation
- 2001-12-10 JP JP2003509461A patent/JP3953461B2/ja not_active Expired - Fee Related
- 2001-12-10 WO PCT/US2001/047677 patent/WO2003003376A1/en active IP Right Grant
- 2001-12-10 CN CNB018234240A patent/CN100345213C/zh not_active Expired - Lifetime
- 2001-12-10 KR KR1020037015468A patent/KR100613317B1/ko not_active IP Right Cessation
- 2001-12-10 DE DE60119995T patent/DE60119995T2/de not_active Expired - Lifetime
- 2001-12-10 EP EP01995491A patent/EP1433179B1/en not_active Expired - Lifetime
-
2002
- 2002-06-28 TW TW91114365A patent/TW574708B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6400629B1 (en) | 2002-06-04 |
CN1522445A (zh) | 2004-08-18 |
KR20040008197A (ko) | 2004-01-28 |
DE60119995D1 (de) | 2006-06-29 |
DE60119995T2 (de) | 2007-05-24 |
ATE327555T1 (de) | 2006-06-15 |
JP2004531019A (ja) | 2004-10-07 |
WO2003003376A1 (en) | 2003-01-09 |
CN100345213C (zh) | 2007-10-24 |
EP1433179B1 (en) | 2006-05-24 |
TW574708B (en) | 2004-02-01 |
EP1433179A1 (en) | 2004-06-30 |
KR100613317B1 (ko) | 2006-08-21 |
EP1433179A4 (en) | 2005-07-06 |
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