JP3007720B2 - 半導体装置の製造方法及び該方法を実施する装置 - Google Patents

半導体装置の製造方法及び該方法を実施する装置

Info

Publication number
JP3007720B2
JP3007720B2 JP3184115A JP18411591A JP3007720B2 JP 3007720 B2 JP3007720 B2 JP 3007720B2 JP 3184115 A JP3184115 A JP 3184115A JP 18411591 A JP18411591 A JP 18411591A JP 3007720 B2 JP3007720 B2 JP 3007720B2
Authority
JP
Japan
Prior art keywords
conductor
anvil
coining
die
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3184115A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04233261A (ja
Inventor
マルチヌス アントニウス マリア ファン ケンペン ヨハネス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips NV, Koninklijke Philips Electronics NV filed Critical Koninklijke Philips NV
Publication of JPH04233261A publication Critical patent/JPH04233261A/ja
Application granted granted Critical
Publication of JP3007720B2 publication Critical patent/JP3007720B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Forging (AREA)
JP3184115A 1990-06-29 1991-06-28 半導体装置の製造方法及び該方法を実施する装置 Expired - Fee Related JP3007720B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9001491A NL9001491A (nl) 1990-06-29 1990-06-29 Werkwijze ter vervaardiging van een halfgeleiderinrichting, en inrichting voor toepassing van de werkwijze.
NL9001491 1990-06-29

Publications (2)

Publication Number Publication Date
JPH04233261A JPH04233261A (ja) 1992-08-21
JP3007720B2 true JP3007720B2 (ja) 2000-02-07

Family

ID=19857336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3184115A Expired - Fee Related JP3007720B2 (ja) 1990-06-29 1991-06-28 半導体装置の製造方法及び該方法を実施する装置

Country Status (6)

Country Link
US (1) US5202289A (OSRAM)
EP (1) EP0463685B1 (OSRAM)
JP (1) JP3007720B2 (OSRAM)
DE (1) DE69112923T2 (OSRAM)
NL (1) NL9001491A (OSRAM)
TW (1) TW218425B (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940006083B1 (ko) * 1991-09-11 1994-07-06 금성일렉트론 주식회사 Loc 패키지 및 그 제조방법
US5288943A (en) * 1993-01-27 1994-02-22 The Whitaker Corporation Method of providing bends in electrical leads, and articles made thereby
JPH0737940A (ja) * 1993-07-22 1995-02-07 Sanken Electric Co Ltd 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112052A (ja) * 1984-06-27 1986-01-20 Hitachi Ltd フラツトパツク部品のリ−ド矯正方法
JPH01192155A (ja) * 1988-01-28 1989-08-02 Mitsui High Tec Inc リードフレームの製造方法
JPH01321663A (ja) * 1988-06-23 1989-12-27 Nec Corp 半導体装置のリード成形装置

Also Published As

Publication number Publication date
EP0463685A1 (en) 1992-01-02
NL9001491A (nl) 1992-01-16
TW218425B (OSRAM) 1994-01-01
DE69112923D1 (de) 1995-10-19
US5202289A (en) 1993-04-13
EP0463685B1 (en) 1995-09-13
DE69112923T2 (de) 1996-04-25
JPH04233261A (ja) 1992-08-21

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees