JP2987081B2 - 半導体装置製造方法 - Google Patents

半導体装置製造方法

Info

Publication number
JP2987081B2
JP2987081B2 JP7122303A JP12230395A JP2987081B2 JP 2987081 B2 JP2987081 B2 JP 2987081B2 JP 7122303 A JP7122303 A JP 7122303A JP 12230395 A JP12230395 A JP 12230395A JP 2987081 B2 JP2987081 B2 JP 2987081B2
Authority
JP
Japan
Prior art keywords
layer
conductive
semiconductor
slice
contact window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7122303A
Other languages
English (en)
Japanese (ja)
Other versions
JPH07321298A (ja
Inventor
デッカー ロナルド
ホデフリダス ラファエル マース ヘンリカス
テオドラス アントニウス ヨハネス ファン デン アインデン ウイルヘルムス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPH07321298A publication Critical patent/JPH07321298A/ja
Application granted granted Critical
Publication of JP2987081B2 publication Critical patent/JP2987081B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Weting (AREA)
JP7122303A 1994-05-24 1995-05-22 半導体装置製造方法 Expired - Lifetime JP2987081B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE09400527 1994-05-24
BE9400527A BE1008384A3 (nl) 1994-05-24 1994-05-24 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met halfgeleiderelementen gevormd in een op een dragerplak aangebrachte laag halfgeleidermateriaal.

Publications (2)

Publication Number Publication Date
JPH07321298A JPH07321298A (ja) 1995-12-08
JP2987081B2 true JP2987081B2 (ja) 1999-12-06

Family

ID=3888174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7122303A Expired - Lifetime JP2987081B2 (ja) 1994-05-24 1995-05-22 半導体装置製造方法

Country Status (8)

Country Link
US (1) US5504036A (https=)
EP (1) EP0684643B1 (https=)
JP (1) JP2987081B2 (https=)
KR (1) KR100348233B1 (https=)
CN (1) CN1061783C (https=)
BE (1) BE1008384A3 (https=)
DE (1) DE69505048T2 (https=)
TW (1) TW288193B (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
EP0770267B1 (en) * 1995-05-10 2002-07-17 Koninklijke Philips Electronics N.V. Method of manufacturing a device, by which method a substrate with semiconductor element and conductor tracks is glued to a support body with metallization
CA2246057C (en) * 1996-01-31 2005-12-20 Cochlear Limited Thin film fabrication technique for implantable electrodes
US5698474A (en) * 1996-02-26 1997-12-16 Hypervision, Inc. High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection
JP2839007B2 (ja) * 1996-04-18 1998-12-16 日本電気株式会社 半導体装置及びその製造方法
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
WO1998019337A1 (en) * 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
EP1503406A3 (en) * 1996-10-29 2009-07-08 Tru-Si Technologies, Inc. Back-side contact pads of a semiconductor chip
US5897371A (en) * 1996-12-19 1999-04-27 Cypress Semiconductor Corp. Alignment process compatible with chemical mechanical polishing
EP1148546A1 (de) * 2000-04-19 2001-10-24 Infineon Technologies AG Verfahren zur Justierung von Strukturen auf einem Halbleiter-substrat
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
JP3788268B2 (ja) * 2001-05-14 2006-06-21 ソニー株式会社 半導体装置の製造方法
TW487958B (en) * 2001-06-07 2002-05-21 Ind Tech Res Inst Manufacturing method of thin film transistor panel
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method
US7831151B2 (en) 2001-06-29 2010-11-09 John Trezza Redundant optical device array
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP4110390B2 (ja) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
US20030189215A1 (en) * 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
US8294172B2 (en) 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
US6841802B2 (en) * 2002-06-26 2005-01-11 Oriol, Inc. Thin film light emitting diode
JP2005150686A (ja) 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
US20080094725A1 (en) * 2004-08-09 2008-04-24 Koninklijke Philips Electronics, N.V. Method for bringing together at least two predetermined quantities of fluid and/or gas
WO2006038150A2 (en) * 2004-10-05 2006-04-13 Koninklijke Philips Electronics N.V. Semiconductor device and use thereof
CN100555589C (zh) * 2005-06-29 2009-10-28 皇家飞利浦电子股份有限公司 制造半导体组件的方法
JP2008078486A (ja) * 2006-09-22 2008-04-03 Oki Electric Ind Co Ltd 半導体素子
GB2492532B (en) * 2011-06-27 2015-06-03 Pragmatic Printing Ltd Transistor and its method of manufacture
GB2492442B (en) * 2011-06-27 2015-11-04 Pragmatic Printing Ltd Transistor and its method of manufacture
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532003A (en) * 1982-08-09 1985-07-30 Harris Corporation Method of fabrication bipolar transistor with improved base collector breakdown voltage and collector series resistance
US4596069A (en) * 1984-07-13 1986-06-24 Texas Instruments Incorporated Three dimensional processing for monolithic IMPATTs
JPS6418248A (en) * 1987-07-13 1989-01-23 Nec Corp Manufacture of semiconductor device
US5081061A (en) * 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers
US5347154A (en) * 1990-11-15 1994-09-13 Seiko Instruments Inc. Light valve device using semiconductive composite substrate
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area

Also Published As

Publication number Publication date
EP0684643A1 (en) 1995-11-29
KR100348233B1 (ko) 2002-11-02
BE1008384A3 (nl) 1996-04-02
DE69505048D1 (de) 1998-11-05
EP0684643B1 (en) 1998-09-30
CN1115118A (zh) 1996-01-17
US5504036A (en) 1996-04-02
JPH07321298A (ja) 1995-12-08
TW288193B (https=) 1996-10-11
DE69505048T2 (de) 1999-05-12
KR950034534A (ko) 1995-12-28
CN1061783C (zh) 2001-02-07

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