JP2022191221A - 表示装置 - Google Patents
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- JP2022191221A JP2022191221A JP2022142914A JP2022142914A JP2022191221A JP 2022191221 A JP2022191221 A JP 2022191221A JP 2022142914 A JP2022142914 A JP 2022142914A JP 2022142914 A JP2022142914 A JP 2022142914A JP 2022191221 A JP2022191221 A JP 2022191221A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
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- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H10K50/80—Constructional details
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- H10K50/84—Passivation; Containers; Encapsulations
- H10K50/844—Encapsulations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
【解決手段】本発明はアクティブ領域に多結晶半導体層を有する第1薄膜トランジスタと酸化物半導体層を有する第2薄膜トランジスタが配置されるので、低消費電力を具現することができ、ベンディング領域に配置される少なくとも一つの開口部とアクティブ領域に配置される多数のコンタクトホールのいずれか一つは深さが同一であるので、開口部とコンタクトホールを同一工程で形成して工程を簡素化することができ、高電位供給ラインと低電位供給ラインが無機絶縁素材の保護膜を挟んで重畳するので、高電位供給ラインと低電位供給ラインのショート不良を防止することができる。
【選択図】図7
Description
104 酸化物半導体層
106、156 ソース電極
108、158 ドレイン電極
130 発光素子
154 多結晶半導体層
162 低電位供給ライン
172 高電位供給ライン
176、LK 信号リンク
180 ストレージキャパシタ
192、194 開口部
Claims (28)
- アクティブ領域を有する基板と;
前記アクティブ領域に配置され、第1半導体層、第1ゲート電極、第1ソース電極及び第1ドレイン電極を有する第1薄膜トランジスタと;
前記アクティブ領域に配置され、第2半導体層、第2ゲート電極、第2ソース電極及び第2ドレイン電極を有する第2薄膜トランジスタと;
前記第1及び第2薄膜トランジスタ上に配置される無機絶縁素材の保護膜と;
上部ストレージ電極及び下部ストレージ電極を有するストレージキャパシタとを含む、表示装置。 - 前記下部ストレージ電極は前記第1薄膜トランジスタの第1ゲート電極と同一平面上に同一素材で形成される、請求項1に記載の表示装置。
- 前記第1半導体層及び前記第2半導体層の間に配置される第1及び第2下部層間絶縁膜をさらに含む、請求項1に記載の表示装置。
- 前記第2半導体層と重畳する遮光層をさらに含む、請求項3に記載の表示装置。
- 前記ストレージキャパシタの前記上部ストレージ電極は前記遮光層と同一層上に同一素材で形成される、請求項4に記載の表示装置。
- 前記第2下部層間絶縁膜及び上部バッファー層は前記遮光層と前記第2半導体層の間に配置される、請求項4に記載の表示装置。
- 前記上部バッファー層は酸化シリコン(SiOx)から形成され、前記第2下部層間絶縁膜は窒化シリコン(SiNx)から形成される、請求項6に記載の表示装置。
- 前記第1ソース及び第1ドレイン電極は前記第2ソース及び第2ドレイン電極と同一平面上に、前記第2ソース及び第2ドレイン電極と同一素材で形成される、請求項3に記載の表示装置。
- 前記第1半導体層は多結晶半導体層からなり、前記第2半導体層は酸化物半導体層からなる、請求項8に記載の表示装置。
- 前記アクティブ領域に配置される多数のコンタクトホールをさらに含む、請求項9に記載の表示装置。
- 前記第1薄膜トランジスタは、
前記多結晶半導体層と重畳する第1ゲート電極と、前記多数のコンタクトホールのうち第1ソースコンタクトホールを介して前記多結晶半導体層と接触する第1ソース電極と、前記多数のコンタクトホールのうち第1ドレインコンタクトホールを介して前記多結晶半導体層と接触する第1ドレイン電極とを含み、
前記第2薄膜トランジスタは、
前記酸化物半導体層と重畳する第2ゲート電極と、前記多数のコンタクトホールのうち第2ソースコンタクトホールを介して前記酸化物半導体層と接触する第2ソース電極と、前記多数のコンタクトホールのうち第2ドレインコンタクトホールを介して前記酸化物半導体層と接触する第2ドレイン電極とを含み、
前記第1及び第2ソース電極は前記第1及び第2ドレイン電極と同一平面上に、前記第1及び第2ドレイン電極と同一素材で形成される、請求項1に記載の表示装置。 - 前記第2ソース及び第2ドレイン電極のそれぞれと前記酸化物半導体層の間に配置される上部層間絶縁膜と;
前記多結晶半導体層と前記酸化物半導体層の間に順次積層される下部ゲート絶縁膜、第1下部層間絶縁膜、第2下部層間絶縁膜及び上部バッファー層とをさらに含み、
前記第1ソース及び第1ドレインコンタクトホールは、前記下部ゲート絶縁膜、前記第1下部層間絶縁膜、前記第2下部層間絶縁膜、前記上部バッファー層及び前記上部層間絶縁膜を貫通して前記多結晶半導体層を露出させ、
前記第2ソース及び第2ドレインコンタクトホールは前記上部層間絶縁膜を貫通して前記酸化物半導体層を露出させる、請求項3に記載の表示装置。 - 前記ストレージ下部電極は前記下部ゲート絶縁膜上に配置され、
前記ストレージ上部電極は前記第1下部層間絶縁膜を挟んで前記ストレージ下部電極と重畳する、請求項12に記載の表示装置。 - 前記基板はベンディング領域をさらに含む、請求項13に記載の表示装置。
- 前記ベンディング領域に配置され、前記多数のコンタクトホールの少なくとも一つと同一の深さを有する少なくとも一つの開口部をさらに含む、請求項14に記載の表示装置。
- 前記少なくとも一つの開口部は、
前記第2ソース及び第2ドレインコンタクトホールと同一の深さを有する第1開口部と、
前記第1ソース及び第1ドレインコンタクトホールより深い深さを有する第2開口部とを含む、請求項15に記載の表示装置。 - 前記基板上に配置されるマルチバッファー層と;
前記マルチバッファー層上に配置される下部バッファー層とをさらに含み、
前記第1開口部は、前記ベンディング領域に配置される前記上部層間絶縁膜を貫通し、
前記第2開口部は、前記ベンディング領域に配置される前記マルチバッファー層、前記下部バッファー層、前記下部ゲート絶縁膜、前記第1下部層間絶縁膜、前記第2下部層間絶縁膜及び前記上部バッファー層を貫通し、
前記ベンディング領域の基板は前記少なくとも一つの開口部によって露出される、請求項16に記載の表示装置。 - 前記第1ソース電極及び第1ドレイン電極と前記第2ソース及び第2ドレイン電極は前記上部層間絶縁膜上に配置される、請求項12に記載の表示装置。
- 前記第1及び第2薄膜トランジスタのいずれか一つと接続される高電位供給ラインと;
前記保護膜を挟んで前記高電位供給ラインと重畳する低電位供給ラインとをさらに含む、請求項15に記載の表示装置。 - 前記第2薄膜トランジスタと接続されるアノード電極と前記低電位供給ラインと接続されるカソード電極とを含む有機発光素子をさらに含み、
前記低電位供給ライン及び前記高電位供給ラインの少なくとも一つはメッシュ状に配置される、請求項19に記載の表示装置。 - 前記上部層間絶縁膜上に配置される第1平坦化層と;
前記第1平坦化層上に配置され、前記第2薄膜トランジスタと前記アノード電極を連結する画素連結電極と;
前記画素連結電極を覆うように配置される第2平坦化層とをさらに含む、請求項20に記載の表示装置。 - 前記低電位供給ラインは、
互いに交差する第1及び第2低電位供給ラインを含み、
前記高電位供給ラインは、
前記第1低電位供給ラインに平行な第1高電位供給ラインと、
前記保護膜及び前記第1平坦化層を挟んで前記前記第2低電位供給ラインと重畳する第2高電位供給ラインとを含む、請求項21に記載の表示装置。 - 前記第2低電位供給ラインは前記画素連結電極と同一平面上に同一素材で形成され、
前記第2高電位供給ラインは前記第2ソース及び第2ドレイン電極と同一平面上に同一素材で形成され、請求項22に記載の表示装置。 - 前記アクティブ領域に配置される信号ラインと接続され、前記開口部によって露出された前記ベンディング領域に配置される信号リンクをさらに含む、請求項23に記載の表示装置。
- 前記開口部によって露出された前記ベンディング領域の前記基板上に、前記基板と接触するように配置され、前記第1及び第2ソース電極と同一素材で形成され信号リンクをさらに含み、
前記第1及び第2平坦化層は前記信号リンクを覆うように配置される、請求項24に記載の表示装置。 - 前記信号リンクは前記開口部によって露出された前記ベンディング領域の前記第1平坦化層上に配置され、前記画素連結電極と同一素材で形成され、
前記第2平坦化層は前記信号リンクを覆うように配置される、請求項24に記載の表示装置。 - 前記有機発光素子を駆動する画素駆動回路をさらに含み、
前記画素駆動回路は、
前記第2薄膜トランジスタからなる駆動トランジスタと;
前記駆動トランジスタと接続され、前記第1薄膜トランジスタからなるスイッチングトランジスタとを含む、請求項20に記載の表示装置。 - 前記画素駆動回路は、
前記第2薄膜トランジスタからなり、前記スイッチングトランジスタと接続された第2スイッチングトランジスタと;
前記第1薄膜トランジスタからなり、前記駆動トランジスタと接続された第3スイッチングトランジスタとさらに含む、請求項27に記載の表示装置。
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JP2019109509A (ja) | 2019-07-04 |
JP7140874B2 (ja) | 2022-09-21 |
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JP7314380B2 (ja) | 2023-07-25 |
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CN110034159B (zh) | 2023-10-13 |
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GB2570796B (en) | 2020-08-26 |
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US11489030B2 (en) | 2022-11-01 |
DE102018132095A1 (de) | 2019-06-19 |
CN117202705A (zh) | 2023-12-08 |
KR20190073848A (ko) | 2019-06-27 |
GB201820727D0 (en) | 2019-01-30 |
US11765937B2 (en) | 2023-09-19 |
CN110034159A (zh) | 2019-07-19 |
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