JP2021170795A - デュアルカラムパラレルccdセンサおよびセンサを用いた検査システム - Google Patents
デュアルカラムパラレルccdセンサおよびセンサを用いた検査システム Download PDFInfo
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Abstract
Description
本出願は、2016年4月6日にChuangほかによって出願された「A DUAL COLUMN−PARALLEL CCD SENSOR AND INSPECTION SYSTEMS USING A SENSOR」というタイトルの米国仮特許出願第62/319,130号の優先権を主張する。
Claims (27)
- イメージセンサであって、
1つ以上のピクセル制御信号に従って第1と第2のイメージ電荷をそれぞれ生成するように構成された第1と第2のピクセルと、
読み出し回路を含み、読み出し回路が、
第1と第2のピクセルからそれぞれ第1と第2のイメージ電荷を受け取るように構成された第1と第2トランスファゲートと、
前記第1と第2のトランスファゲートからそれぞれ前記第1と第2のイメージ電荷を受け取るように構成された第3と第4トランスファゲートと、
前記第3と第4トランスファゲートに結合された加算ゲートと、
前記加算ゲートに結合された出力回路と、を備え、
前記第1トランスファゲートと前記第4トランスファゲートが結合され、前記第2トランスファゲートと前記第3トランスファゲートが結合されて、その結果、前記第1トランスファゲートに印加された第1トランスファゲート制御信号が前記第4トランスファゲートに実質的に同時に印加され、また、前記第2トランスファゲートに印加された第2トランスファゲート制御信号が前記第3トランスファゲートに実質的に同時に印加され、
前記加算ゲートは、第1の時間周期中に前記第3トランスファゲートから前記第1のイメージ電荷を受け取り、引き続いて加算ゲート制御信号に従って前記第1のイメージ電荷を前記出力回路に移動させるように構成され、前記加算ゲートはさらに、第2の時間周期中に前記第4トランスファゲートから前記第2のイメージ電荷を受け取り、引き続いて前記加算ゲート制御信号に従って前記第2のイメージ電荷を前記出力回路に移動させるように構成されるイメージセンサ。 - 前記出力回路が、前記第1と第2のイメージ電荷を受け取って格納するように構成された浮遊拡散と、前記浮遊拡散に結合されて、前記第1のイメージ電荷が前記浮遊拡散に格納されたときに第1の出力電圧信号を生成し、前記第2のイメージ電荷が前記浮遊拡散に格納されたときに第2の出力電圧信号を生成するように構成された増幅器を備えている、請求項1に記載のセンサ。
- さらに、偶数個の列に配置されたピクセルのアレイを備え、
前記読み出し回路が複数の読み出し構造を含み、各前記読み出し構造は前記列のうち関連するペアに接続され、4つのトランスファゲート、1つの加算ゲートおよび1つの増幅器を含む、請求項1に記載のセンサ。 - 各前記読み出し構造の前記増幅器は金属配線を備え、異なる増幅器の金属配線の静電容量は実質的に同じである、請求項3に記載のセンサ。
- 各前記増幅器は金属配線を備え、異なる増幅器の金属配線の面積は実質的に等しい、請求項3に記載のセンサ。
- 前記ピクセルのアレイはピクセルの1つ以上の行からなる、請求項3に記載のセンサ。
- イメージセンサであって、
半導体基板と、
前記基板に形成され、V字形融合区分によって第3の細長い部分に接続された平行な第1と第2の細長い部分を含むY字形埋込拡散と、
前記第1と第2の細長い部分の上にそれぞれ形成された複数のピクセルゲート構造と、
前記第1と第2の細長い部分の上にそれぞれ形成され、前記ピクセルゲート構造と前記V字形融合区分の間に配置された第1と第2トランスファゲート構造と、
前記第1と第2の細長い部分の上にそれぞれ形成され、前記第1と第2トランスファゲート構造と前記V字形融合区分の間に配置された第3と第4トランスファゲート構造と、
前記V字形融合区分の上に形成された加算ゲート構造と、
前記第3の細長い部分に結合された出力回路と、を備え、
前記第1トランスファゲート構造と前記第4トランスファゲート構造は、前記第1トランスファゲート構造に印加された第1の制御信号が前記第4トランスファゲート構造に実質的に同時に印加されるように結合され、
前記第2トランスファゲート構造と前記第3トランスファゲート構造は、前記第2トランスファゲート構造に印加された第2の制御信号が前記第3トランスファゲート構造に実質的に同時に印加されるように結合される、イメージセンサ。 - 前記第1トランスファゲート構造と前記第4トランスファゲート構造は、前記第1トランスファゲート構造に印加された前記第1の制御信号が前記第1の導電性リンク構造によって前記第4トランスファゲート構造に伝送されるように、第1の導電性リンク構造によって接続されている、請求項7に記載のイメージセンサ。
- 前記第1の導電性リンク構造は金属および多結晶シリコンのうち1つを含む請求項8に記載にイメージセンサ。
- 前記第1トランスファゲート構造、前記第4トランスファゲート構造および前記第1の導電性リンク構造は一体型複合多結晶シリコン構造を備える、請求項8に記載にイメージセンサ。
- 前記加算ゲート構造は、第1の時間周期中に前記第1の細長い部分から第1のイメージ電荷を受け取り、続いて前記第1のイメージ電荷を加算ゲート制御信号に従って前記第3の細長い部分に移動させるように構成され、前記加算ゲートはさらに、第2の時間周期中に前記第2の細長い部分から第2のイメージ電荷を受け取り、続いて前記第2のイメージ電荷を加算ゲート制御信号に従って前記第3の細長い部分に移動させるように構成されている、請求項7に記載にイメージセンサ。
- 前記加算ゲート構造は、前記第1と第2の細長い部分に面した上流縁と、前記第3の細長い部分に面した下流縁を有する先細の多結晶シリコン構造を備え、前記上流縁の長さは前記下流縁の長さより大きい、請求項7に記載にイメージセンサ。
- さらに、前記加算ゲート構造と前記第3の細長い部分の間に配置された先細の出力ゲート構造を備えている請求項7に記載にイメージセンサ。
- 前記出力回路が、
前記第3の細長い部分に形成された浮遊拡散と、
前記基板上に配置され、導電性構造によって前記浮遊拡散に作動的に結合された増幅器を備えている、請求項7に記載にイメージセンサ。 - 前記増幅器が第1段ゲイントランジスタを備え、
前記導電性構造が、コンタクトホールを貫通して前記浮遊拡散に延出する下部ポリ部と、前記下部ポリ部から延出する水平ポリ部を備え、前記水平ポリ部の部分は前記第1段ゲイントランジスタのゲート構造を形成する、
請求項14に記載にイメージセンサ。 - 試料を検査する方法であって、方法が、
放射線を試料に指向させて集束させ、
試料からの放射線を受け取って、受け取った放射線をイメージセンサに指向させ、前記センサはデュアルカラムパラレルCCDを備え、
前記受け取りと同時に前記試料を放射線に相対して移動させ、
前記イメージセンサを、放射線に相対した前記試料の運動に同期化されたラインクロック信号で駆動し、前記ラインクロック信号は、電荷をイメージセンサの1つの行から隣接する行に移動させ、
前記イメージセンサのバッファゲートの行をバッファクロック信号で駆動し、前記バッファクロック信号は、電荷を、イメージセンサの縁の行からバッファゲートの行に移動させ、
第1のトランスファクロック信号で、前記イメージセンサのトランスファゲートの第1行内の第1のトランスファゲートと、前記イメージセンサのトランスファゲートの第2行内の第1のトランスファゲートを駆動し、
第2のトランスファクロック信号で、前記イメージセンサのトランスファゲートの第1行内の第2のトランスファゲートと、前記イメージセンサのトランスファゲートの第2行内の第2のトランスファゲートを駆動し
前記イメージセンサの出力信号をアナログデジタルコンバータ(ADC)でデジタル化し、
前記ADCを、前記ラインクロック信号の周波数の二倍より大きいクロック周波数で駆動することを含み、
前記第1のトランスファクロック信号は電荷を前記トランスファゲートの第1行内の第1のトランスファゲートから前記トランスファゲートの第2行内の第2のトランスファゲートに移動させ、
前記第2のトランスファクロック信号は電荷を前記トランスファゲートの第1行内の第2のトランスファゲートから前記トランスファゲートの第2行内の第1のトランスファゲートに移動させる、方法。 - 前記第1のトランスファクロック信号はさらに、電荷をトランスファゲートの第2行内の第1のトランスファゲートから加算ゲートに移動させ、
前記第2のトランスファクロック信号はさらに、電荷をトランスファゲートの第2行内の第2のトランスファゲートから加算ゲートに移動させる、請求項16に記載の方法。 - さらに、前記イメージセンサのリセットゲートを、実質的に一定のパルス幅で駆動し、前記リセットゲートは、加算ゲートからの、または、加算ゲートに接続された出力ゲートからの電荷を受け取るように構成された浮遊拡散に接続され、
リセットゲートパルスの後で、出力信号を実質的に一定の時間間隔でサンプリングするためにADCを起動させることを含む請求項16に記載の方法。 - さらに、前記イメージセンサのトランスファゲートの第3行内の第1のトランスファゲートを第1のトランスファクロック信号で駆動し、前記トランスファゲートの第3行内の第2のトランスファゲートを第2のトランスファクロック信号で駆動し、前記トランスファゲートの第1、第2および第3行内の第3のトランスファゲートを第3のトランスファクロック信号で駆動することを含む請求項16に記載の方法。
- 前記ラインクロックの周波数は相対運動の速度が変動するにつれ変動する、請求項16に記載の方法。
- さらに、バッファクロック信号をラインクロックと同期化された状態に保つために、バッファクロック信号の1つのサイクルを休止またはスキップすることを含む、請求項20に記載の方法。
- さらに、バッファクロック信号をラインクロックと同期化された状態に保つためにバッファクロック信号の1つのサイクルを遅延させるまたは広げることを含む、請求項20に記載の方法。
- 試料を検査するための検査システムであって、前記検査システムが、
放射線を生成する放射線ソースと、
放射線を試料に指向させて集束させ、試料から反射または散乱された放射線を受け取って、受け取った放射線をデュアルカラムパラレルCCDを備えるイメージセンサに指向させるための光学素子と、
前記検査システムを制御し、前記イメージセンサからイメージデータを受け取り、前記イメージデータを解析して、試料上の欠陥を位置特定するか、または試料の寸法を測定するためのコンピューティングシステムと、
を備え、
前記デュアルカラムパラレルCCDが、偶数個の列に配置された長方形または矩形のピクセルのアレイを備え、
さらに、ピクセルのアレイの各列から電荷を受け取るように構成された出力構造を備え、前記出力構造が、
第1行と第2行のトランスファゲートを備え、前記第2行のトランスファゲートは前記第1行のトランスファゲートから電荷を受け取るように構成され、
前記第2行のトランスファゲートから電荷を受け取るように構成された一行の加算ゲートと、
一行の出力ゲートを備え、各出力ゲートは対応する前記加算ゲートから電荷を受け取って電荷を対応する浮遊拡散および出力増幅器に伝送するように構成されている、検査システム。 - 前記光学素子がさらに、前記試料上のラインを照明するように構成されている請求項23に記載の検査システム。
- 前記光学素子がさらに、前記試料の垂直および斜めの照明両方向けに構成されている請求項23に記載の検査システム。
- 前記試料はパターンなしウェハを含む請求項25に記載の検査システム。
- 前記出力構造はさらに、前記ピクセルのアレイの各列から電荷を受け取ってこれらの電荷を前記第1行のトランスファゲートに伝送するように構成された一行のバッファゲートを備える、請求項25に記載の検査システム。
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