JP2019504490A5 - - Google Patents

Download PDF

Info

Publication number
JP2019504490A5
JP2019504490A5 JP2018531326A JP2018531326A JP2019504490A5 JP 2019504490 A5 JP2019504490 A5 JP 2019504490A5 JP 2018531326 A JP2018531326 A JP 2018531326A JP 2018531326 A JP2018531326 A JP 2018531326A JP 2019504490 A5 JP2019504490 A5 JP 2019504490A5
Authority
JP
Japan
Prior art keywords
semiconductor wafer
bend
warp
depositing
warpage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018531326A
Other languages
English (en)
Japanese (ja)
Other versions
JP6952697B2 (ja
JP2019504490A (ja
Filing date
Publication date
Priority claimed from US15/379,759 external-priority patent/US9978582B2/en
Application filed filed Critical
Publication of JP2019504490A publication Critical patent/JP2019504490A/ja
Publication of JP2019504490A5 publication Critical patent/JP2019504490A5/ja
Priority to JP2021157544A priority Critical patent/JP7025589B2/ja
Application granted granted Critical
Publication of JP6952697B2 publication Critical patent/JP6952697B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2018531326A 2015-12-16 2016-12-16 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体 Expired - Fee Related JP6952697B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021157544A JP7025589B2 (ja) 2015-12-16 2021-09-28 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562268262P 2015-12-16 2015-12-16
US62/268,262 2015-12-16
US15/379,759 2016-12-15
US15/379,759 US9978582B2 (en) 2015-12-16 2016-12-15 Methods for improving wafer planarity and bonded wafer assemblies made from the methods
PCT/US2016/067379 WO2017106788A1 (en) 2015-12-16 2016-12-16 Methods for improving wafer planarity and bonded wafer assemblies made from the methods

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021157544A Division JP7025589B2 (ja) 2015-12-16 2021-09-28 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体

Publications (3)

Publication Number Publication Date
JP2019504490A JP2019504490A (ja) 2019-02-14
JP2019504490A5 true JP2019504490A5 (enExample) 2020-01-30
JP6952697B2 JP6952697B2 (ja) 2021-10-20

Family

ID=59057725

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018531326A Expired - Fee Related JP6952697B2 (ja) 2015-12-16 2016-12-16 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体
JP2021157544A Expired - Fee Related JP7025589B2 (ja) 2015-12-16 2021-09-28 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2021157544A Expired - Fee Related JP7025589B2 (ja) 2015-12-16 2021-09-28 ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体

Country Status (6)

Country Link
US (1) US9978582B2 (enExample)
JP (2) JP6952697B2 (enExample)
KR (1) KR20180095609A (enExample)
CN (1) CN108604572A (enExample)
TW (1) TWI765874B (enExample)
WO (1) WO2017106788A1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10692843B2 (en) * 2013-12-04 2020-06-23 3M Innovative Properties Company Flexible light emitting semiconductor device with large area conduit
US10847419B2 (en) * 2018-03-14 2020-11-24 Raytheon Company Stress compensation and relief in bonded wafers
CN108649021B (zh) * 2018-07-19 2024-07-26 长江存储科技有限责任公司 晶圆翘曲调整结构及其形成方法
WO2020034138A1 (en) * 2018-08-16 2020-02-20 Yangtze Memory Technologies Co., Ltd. Wafer flatness control using backside compensation structure
JP2020047617A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 基板処理装置、半導体装置の製造方法、および被加工基板
WO2020068254A1 (en) * 2018-09-25 2020-04-02 Applied Materials, Inc. Methods and apparatus to eliminate wafer bow for cvd and patterning hvm systems
US10896821B2 (en) * 2018-09-28 2021-01-19 Lam Research Corporation Asymmetric wafer bow compensation by physical vapor deposition
KR102746093B1 (ko) * 2018-09-28 2024-12-23 램 리써치 코포레이션 비대칭 웨이퍼 보우 보상
JP2020161685A (ja) * 2019-03-27 2020-10-01 東京エレクトロン株式会社 成膜装置および成膜方法
JP7259527B2 (ja) * 2019-04-26 2023-04-18 富士電機株式会社 半導体基板の製造方法および半導体装置の製造方法
US10790296B1 (en) * 2019-05-21 2020-09-29 Sandisk Technologies Llc Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer
KR102767982B1 (ko) * 2019-10-15 2025-02-14 에스케이하이닉스 주식회사 웨이퍼 지지 구조체
CN111048429B (zh) * 2019-12-23 2022-05-27 武汉新芯集成电路制造有限公司 一种晶圆键合方法
US12272608B2 (en) 2020-01-03 2025-04-08 Lam Research Corporation Station-to-station control of backside bow compensation deposition
WO2021154641A1 (en) * 2020-01-30 2021-08-05 Lam Research Corporation Uv cure for local stress modulation
FR3121548B1 (fr) * 2021-03-30 2024-02-16 Soitec Silicon On Insulator Procede de preparation d’un substrat avance, notamment pour des applications photoniques
CN116368952A (zh) 2021-06-30 2023-06-30 长江存储科技有限责任公司 三维存储器装置及其形成方法
WO2023272627A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
WO2023272638A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
WO2023272592A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
CN115803882A (zh) 2021-06-30 2023-03-14 长江存储科技有限责任公司 三维存储器装置及其形成方法
CN116018889A (zh) 2021-06-30 2023-04-25 长江存储科技有限责任公司 三维存储器装置及其形成方法
WO2023272634A1 (en) 2021-06-30 2023-01-05 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices
CN113906542A (zh) * 2021-08-30 2022-01-07 长江存储科技有限责任公司 使用背面膜层沉积和激光退火的晶圆应力控制
CN115036204A (zh) * 2022-05-07 2022-09-09 上海华力集成电路制造有限公司 通过降低晶圆翘曲度提高bsi工艺稳定性的方法
TW202431354A (zh) * 2022-09-28 2024-08-01 美商應用材料股份有限公司 應力管理期間全域曲率的校正
US20240266230A1 (en) * 2023-02-08 2024-08-08 Applied Materials, Inc. Optimized film deposition and ion implantation for mitigation of stress and deformation in substrates
CN117373908A (zh) * 2023-10-09 2024-01-09 物元半导体技术(青岛)有限公司 调整晶圆翘曲度的方法、光刻方法及半导体结构
US12435964B2 (en) 2023-11-16 2025-10-07 Tokyo Electron Limited Contactless capacitive measurement tool with improved throughput and accuracy
CN118263137B (zh) * 2024-05-29 2025-07-25 浙江创芯集成电路有限公司 半导体结构的形成方法
DE102024117104A1 (de) * 2024-06-18 2025-12-18 Ligentec Sa Photonisch integrierte Schaltung und Verfahren zur Herstellung

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4790920A (en) 1985-12-20 1988-12-13 Intel Corporation Method for depositing an al2 O3 cap layer on an integrated circuit substrate
US4830984A (en) * 1987-08-19 1989-05-16 Texas Instruments Incorporated Method for heteroepitaxial growth using tensioning layer on rear substrate surface
JPH01256126A (ja) * 1988-04-06 1989-10-12 Sumitomo Electric Ind Ltd 半導体装置の製造方法
US5286671A (en) 1993-05-07 1994-02-15 Kulite Semiconductor Products, Inc. Fusion bonding technique for use in fabricating semiconductor devices
JPH08111409A (ja) * 1994-10-12 1996-04-30 Rohm Co Ltd 半導体装置の製法
JPH08227834A (ja) * 1995-02-21 1996-09-03 Sony Corp 半導体ウェーハ及びその製造方法
US6652356B1 (en) 1999-01-20 2003-11-25 Shin-Etsu Handotai Co., Ltd. Wire saw and cutting method
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US20070194342A1 (en) 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8557681B2 (en) * 2006-10-30 2013-10-15 International Rectifier Corporation III-nitride wafer fabrication
US8664747B2 (en) * 2008-04-28 2014-03-04 Toshiba Techno Center Inc. Trenched substrate for crystal growth and wafer bonding
US20100314725A1 (en) * 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
JP5522263B2 (ja) * 2010-09-28 2014-06-18 株式会社村田製作所 圧電デバイス、圧電デバイスの製造方法
WO2012043615A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイスの製造方法
JP2013542599A (ja) * 2010-09-30 2013-11-21 フリースケール セミコンダクター インコーポレイテッド 半導体ウェハを処理するための方法、半導体ウェハおよび半導体デバイス
JP5642628B2 (ja) * 2011-05-27 2014-12-17 東京エレクトロン株式会社 基板反り除去装置、基板反り除去方法及び記憶媒体
JP5418564B2 (ja) * 2011-09-29 2014-02-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの反りを算出する方法、及び貼り合わせｓｏｉウェーハの製造方法
US8900969B2 (en) * 2012-01-27 2014-12-02 Skyworks Solutions, Inc. Methods of stress balancing in gallium arsenide wafer processing
KR20140104062A (ko) * 2013-02-15 2014-08-28 삼성전자주식회사 P형 질화물 반도체 제조방법 및 이를 이용한 질화물 반도체 발광소자 제조방법
US9184041B2 (en) * 2013-06-25 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with backside structures to reduce substrate warp
CN105448762A (zh) * 2014-08-28 2016-03-30 中国科学院微电子研究所 一种衬底翘曲度的调整方法

Similar Documents

Publication Publication Date Title
JP2019504490A5 (enExample)
FR2957280B1 (fr) Procede de fabrication d'un complexe metallique
TW201642326A (en) Structure and formation method of semiconductor device structure
EP4293707A3 (en) Direct and sequential formation of monolayers of boron nitride and graphene on substrates
JP2012114426A5 (ja) 半導体装置
TW201611949A (en) Polishing pad and method for making the same
JP2013038399A5 (ja) 半導体装置
JP2013153160A5 (ja) 半導体装置の作製方法
EP3144960A3 (en) Semiconductor device
JP2017017320A5 (enExample)
MX376363B (es) Acristalamiento provisto con una pila de capas delgadas para proteccion solar.
JP2015518270A5 (enExample)
WO2013134592A3 (en) Atomic layer deposition strengthening members and method of manufacture
PL412520A1 (pl) Sposób wytwarzania folii grafenowej o zadanej liczbie warstw grafenu
JP2013518445A5 (enExample)
WO2015082697A3 (en) Bearing element and method for manufacturing a bearing element
JP2018537305A5 (enExample)
JP2013243343A5 (enExample)
JP2020510284A5 (enExample)
JP2013215813A5 (enExample)
MY192661A (en) Semiconductor processing tape
WO2015126575A3 (en) Silicon carbide semiconductor device, and methods for manufacturing thereof
PH12015502841A1 (en) Tib2 layers and use thereof
JP2009138229A5 (enExample)
PT3875248T (pt) Método para produzir uma estrutura tridimensional numa superfície de um substrato plano