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Definitions

• the invention generally relates to semiconductor fabrication methods. More specifically, the invention relates to: 1) a method for enhancing the flatness, i.e.; the planarity of a warped or bowed semiconductor wafer using oxide deposition techniques to increase semiconductor wafer and die yields, and, 2) a bonded semiconductor wafer assembly made from the method.
• GaN-on- sapphire semiconductor wafers, substrates or templates are common in photonic applications but often have surface non-planarity.
• the undesirable non-planarity of a semiconductor wafer can be characterized by warp and/or bowing.
• Typical warp and/or bow measurements on semiconductor wafers are affected by measurement method and edge exclusion region definition. The smaller the edge exclusion region, the higher the measured warp and/or bow.
• Semiconductor wafer warp and/or bow are also affected by the diameter of the semiconductor wafer and by the thicknesses of the underlying substrate and grown epitaxial layers on standard semiconductor wafers.
• Semiconductor wafer warp may be on the order of 100 ⁇ or greater across the surface of a 4-in.
• warp in a substrate is desirably reduced to at least less than 80 ⁇ across a 4-in. semiconductor wafer and greater reductions of warp/bow further improve semiconductor wafer bonding properties in subsequent processing steps.
• the warp of a 4-in. photonic semiconductor wafer should be less than 80 ⁇ to be accepted by a typical photolithographic stepper, such as a Canon stepper for example, in terms of mechanical handling (e.g.; vacuum arm and chuck), which in turn improves the local planar focus.
• a typical photolithographic stepper such as a Canon stepper for example
• mechanical handling e.g.; vacuum arm and chuck
• semiconductor wafer bow negatively affects vacuum arm pick up of the semiconductor wafer (from a cassette for example) and excessive
• An inexpensive process for reducing non-planarity and improving semiconductor wafer shape profile of the aforementioned semiconductor wafers is needed to improve yields in subsequent semiconductor wafer processing steps.
• Fig. 1A is a process flow chart of a preferred set of steps of the method of the invention.
• Fig. IB is a cross-section of a semiconductor wafer having a convex warp or bow.
• Fig. 1C is a cross-section of the semiconductor wafer after having a thin film layer deposited on its second surface.
• Fig. ID illustrates a pair of semiconductor wafers that have been processed according to the method of the invention and fusion bonded to form a semiconductor wafer assembly.
• Fig. 2A is a wafer planarity map of a semiconductor wafer with a warp or bow that has not been processed according to the method of this invention.
• Fig. 2B is a wafer planarity map of the semiconductor wafer of Fig. 2A after being processed according to the method of the invention.
• Fig. 3A is a second surface of a semiconductor wafer that has been patterned with a thin film layer according to a method of the invention.
• Fig. 3B is a second surface of a semiconductor wafer that has been patterned with two thin film layers according to another method of the invention.
• a preferred method of this invention comprises the step of an engineered patterning and deposition of a compressive dielectric material thin film layer (such as, without limitation, a PECVD oxide such as silicon oxide-Si0 2 ) of a predetermined thickness, pattern and composition, or a tensile layer of such material, to provide an offsetting compressive or tensile force across the surface of a semiconductor wafer to reduce undesirable warp and bow in the semiconductor wafer.
• a compressive dielectric material thin film layer such as, without limitation, a PECVD oxide such as silicon oxide-Si0 2
• the planarizing effect of the above offsetting dielectric layer has been measured by Applicant herein and has been shown to materially improve the warp and/or bow properties of a non-planar photonic semiconductor wafer, resulting in improved yields during follow-on photolithography and semiconductor wafer bonding steps.
• a method for reducing warp and/or bow in a semiconductor wafer comprising the steps of providing a semiconductor wafer 1 having a first surface and a second surface 10 wherein the surface profile of semiconductor wafer 1 comprises a warp and/or a bow as illustrated in Fig. IB.
• the first surface of the semiconductor wafer will be the surface of the
• a thin film layer 15 having a predetermined thickness, pattern or coefficient of thermal expansion (“CTE") is deposited on the second surface 10 to induce a predetermined strain-modifying compressive or tensile force or a compressive and tensile force on and across the second surface 10 of semiconductor wafer 1.
• CTE coefficient of thermal expansion
• the thin film layer 15 is deposited on the second surface 10 to induce a predetermined strain-modifying tensile force on and across the second surface 10 of semiconductor wafer 1, causing the semiconductor wafer to
• the thin film layer 15 may comprise an oxide layer, metal layer, metal oxide layer or ceramic material layer or equivalent layer materials.
• the thickness, pattern or CTE of thin film layer 15 may be calculated and determined based on the measured warp and/or bow.
• thin film layer 15 may comprise an S1O2 layer.
• Thin film layer 15 may be deposited using a PECVD process.
• Thin film layer 15 may have a thickness of about 1 ⁇ per about 5 ⁇ to about 8 ⁇ of warp or bow.
• Semiconductor wafer 1 may comprise a GaN layer on a sapphire semiconductor wafer, substrate or template.
• a 4-in. semiconductor wafer desirably has a warp of less than about 80 ⁇ for processing in industry-standard stepper equipment.
• acceptable warpage or bowing is typically desired to be less than about 40-50 ⁇ warp or bow across the surface of the semiconductor wafer.
• Warpage or bowing below 40-50 ⁇ semiconductor wafer warp/bow is further desired, particularly for subsequent semiconductor wafer fusion bonding applications. Any remaining warpage/bow is desirably convex across the first surface of the semiconductor wafer.
• semiconductor wafers that includes bonding with other semiconductor wafers demands a high level of wafer planarization.
• the bonding of 4-in. semiconductor wafers using either direct fusion bonding or eutectic bonding would typically require less than 40- 50 ⁇ warp or bow across the surface of the semiconductor wafers, with flatter
• semiconductor wafers typically yielding reduced edge exclusion in the bonding process.
• conventional photonic semiconductor wafers such as Ill-nitride semiconductor wafers on sapphire or silicon substrates, are frequently supplied with a semiconductor wafer surface profile having a least some degree of warpage and/or bowing.
• Applicant herein discloses a method for minimizing semiconductor wafer warp and bowing.
• the steps are carried out using a deposition process with a plasma-enhanced chemical vapor deposition (PECVD) tool to deposit a silicon dioxide or "SiC " ("oxide” herein), thin film layer 15 having a predetermined thickness and composition on second (non-circuit bearing) surface 10 of semiconductor wafer 1.
• PECVD plasma-enhanced chemical vapor deposition
• SiC silicon dioxide
• the invention is not limited to the use of S1O2 as a planarizing thin film layer 15 and different materials, such as those noted below and their equivalents, can be used as planarizing thin film layers 15 in the instant invention.
• the atomic spacing of the oxide thin film layer 15 deposited on the second surface 10 of the semiconductor wafer 1 is greater than the atomic spacing of the substrate or template, such as sapphire, upon which the photonic material, such as Ill-nitride material, is deposited.
• the different atomic spacing creates a lattice mismatch between the two materials, resulting in an induced tension on the second surface of the semiconductor wafer 1.
• the deposited oxide thin film layer 15 seeks a larger surface area than is provided by the sapphire substrate or template, creating a strain tending to enlarge the second surface of the semiconductor wafer, which in turn tends to flatten the sapphire as the oxide thin film layer 15 seeks to expand the second surface area 10.
• the layer 15 in this and other embodiments acts as a strain- modifying layer reducing the warp or bow across the first and second surfaces of the semiconductor wafer compared to the warp or bow across the surface of the semiconductor wafer before the layer 15 is deposited.
• thermal expansion mismatch-related strain plays a significant role in changing a semiconductor wafer 1 shape which
• CTE coefficient of thermal expansion
• CTE itself is a physical phenomenon and is exploited in a preferred embodiment as a semiconductor wafer planarizing method, particularly when certain thin film layer 15 materials are deposited on a semiconductor wafer 1 surface at a temperature other than room temperature.
• CTE occurs due to the fact that as temperature increases, higher level quantum states in a material become more populated in the asymmetric potential wells. These higher level quantum states have probability densities that increase at values greater than the equilibrium radius. In other words, on a time average, atoms spend more time at a farther distance away from each other as temperature increases. If there is a CTE mismatch between two materials, the amount of average atomic spacing change with temperature is different for each material.
• CTE film stress non-lattice mismatch
• a film with a larger CTE than the host substrate is deposited at an elevated temperature. At the deposition temperature, the structure is stress-neutral but once the structure cools, thin film layer 15 will contract more than the substrate, causing thin film layer 15 to be in tensile or compressive stress (depending on the film material CTE) across second surface 10.
• Deposition Pressure about 100 to 2000 mTorr
• RF Power about 100 to 1000W at about 13.56 MHz
• Deposition rate about 500 to 5000 A/min
• BOE 1 Buffered Oxide Etchant
• rate of resultant oxide about 500 to 5000
• A/min Oxide Film Stress about 100 to 1000 MPa compressive on Si(100)
• the deposited oxide thin film layer 15 preferably has a non-uniformity of less than about 10%. Processing temperatures during oxide thin film layer 15 deposition are not a substantial processing constraint as it has been observed that an oxide thin film layer 15 deposited within the range of about 300 °C and 400 °C exhibits an acceptable compressive effect.
• Figs. 2A and 2B a graphical depiction of warp and bow adjustment data from semiconductor wafer metrology measurements conducted using Sigmatech backpressure semiconductor wafer shape measurement equipment is set forth showing planarity improvement from an unprocessed semiconductor wafer (Fig. 2A) to the same
• Total thickness variation or "TTV” can increase or decrease roughly by the non- uniformity of the deposited oxide thin film layer 15 and such semiconductor wafer 1 thickness scales at about 80-90% of the target deposited oxide thickness.
• semiconductor wafer 1 it is preferable that semiconductor wafer 1 not be exposed to buffered oxide etchants or "BOE" and HF, unless a warp and bow adjust oxide thin film layer 15 deposition step is repeated.
• deposited thin film layer 15 oxide thickness uniformity may have some effect on subsequent processing steps such as laser liftoff (LLO) uniformity, for example.
• LLO uniformity may be affected by the quarter-wavelength interference condition of the UV laser light caused by oxide thin film layer 15 uniformity and not by UV absorption of the layer 15.
• LLO uniformity may be affected by the quarter-wavelength interference condition of the UV laser light caused by oxide thin film layer 15 uniformity and not by UV absorption of the layer 15.
• the deposited thin film layer 15 is thus not limited to silicon dioxide material; any suitable thin film layer 15 that may be deposited on a semiconductor wafer 1 surface at a predetermined thickness that is sufficient to induce a predetermined compressive, tensile force or a compressive and tensile force due to lattice mismatch or differing CTEs on the second surface 10, may be used.
• the thin film layer 15 is patterned to form elongated strips of the thin film layer, which provides a dominant axis for the strain-modifying effect, whether the thin film layer 15 is chosen to exert compressive forces or tensile forces on the adjacent surface 10 of the semiconductor wafer 1. This can be useful when the bow or warp is about a single axis, or predominately about a single axis. If however the bow or warp is about two axes, but unequal, a second patterned thin film layer 15 may be deposited and oriented about a second axis as shown in Fig. 3B.
• the vertical and horizontal strips may be of the same or different thin film layer materials.
• the bow or warp may be in opposite directions about the two axes, in which case different thin film layer materials will be used, one to induce compressive forces on the adjacent
• Silicon oxide is well-suited for such applications because it is simple to deposit on a semiconductor wafer 1 surface and can be grown in a stress state that reshapes the bow and warp of semiconductor wafer 1 but in alternative embodiments, materials such as silicon nitride, ceramic, metal, or metal oxide thin film layers 15 may be used and are contemplated as within the scope of the method of the invention.
• the above-referenced semiconductor wafer 1 may be regarded as having a generic shape and the methods of this invention function to flatten any generic substrate shape by the deposition of a strain-modifying or compression-modifying thin film layer 15 or films on second surface 10 of semiconductor wafer 1.
• the primary variables for the thin film layer are material, thickness and thin film layer pattern, together with the coefficient of thermal expansion that is a characteristic of the material, which in some cases may be different for different film thicknesses of interest for the same material.
• semiconductor wafer 1 In the previously-discussed preferred embodiment of c-plane GaN-on- sapphire, semiconductor wafer 1, as viewed with epitaxial surface up, often tends to be fairly uniformly convex, i.e.; the highest point is toward the center of the GaN surface. In such instances, the earlier-described deposition of a blanket compressive oxide thin film layer 15 on the second surface of semiconductor wafer 1 is particularly effective. It is expressly noted however that deposited thin film layer 15 need not be limited to an S1O2 material and that the deposited thin film layer material may be any material that imparts an opposite curvature to semiconductor wafer 1 as compared to the GaN or semiconductor wafer material.
• a deposited thin film layer 15 may be applied that imparts tensile stress to the sapphire.
• GaN itself is a suitable candidate for this embodiment of the invention.
• this invention enables a reduction in the bow along one axis but may increase it in the perpendicular direction.
• a "shadow mask" as is known in the semiconductor arts, may be utilized to selectively deposit a strain- modifying thin film layer 15 having predetermined strain-modifying or tensile
• An equivalent effect may also be achieved by depositing a blanket planarizing thin film layer 15 to second surface 10 of semiconductor wafer 1, patterning semiconductor wafer 1 using photolithography with a predetermined thin film layer 15 pattern such as the exemplar pattern illustrated in Fig. 4, and then selectively removing predetermined areas or portions of the planarizing thin film layer 15 to induce a desired change in the wafer planarity.
• a user may deposit a compressive thin film layer 15 oxide as strips consisting of, for example, two-thirds of the semiconductor wafer area and, for example, a tensile nitride on the central third of semiconductor wafer 1 to modify the shape differently along different axes (Figs. 3A and 3B).
• the differing or varying compressive/tensile layer pattern may be determined using, for instance, strain modeling software based on a given semiconductor wafer shape to model an optimum modifying thin film layer or layers 15 combination pattern for a particular semiconductor wafer bow.

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