TWI682524B - 矽晶圓 - Google Patents
矽晶圓 Download PDFInfo
- Publication number
- TWI682524B TWI682524B TW107120956A TW107120956A TWI682524B TW I682524 B TWI682524 B TW I682524B TW 107120956 A TW107120956 A TW 107120956A TW 107120956 A TW107120956 A TW 107120956A TW I682524 B TWI682524 B TW I682524B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- silicon wafer
- bending
- orientation
- silicon
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 80
- 239000010703 silicon Substances 0.000 title claims abstract description 80
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 230000005856 abnormality Effects 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 140
- 238000005452 bending Methods 0.000 description 56
- 239000010410 layer Substances 0.000 description 34
- 239000013078 crystal Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 230000001629 suppression Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 150000003376 silicon Chemical class 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002798 spectrophotometry method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02027—Setting crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mechanical Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Formation Of Insulating Films (AREA)
Abstract
本發明提供一種矽晶圓,能夠減低裝置製造步驟中產生的晶圓彎曲,沒有問題地實施因為晶圓大幅彎曲而會產生異常的後續步驟。本發明的矽晶圓,在裝置製造步驟中形成構成半導體裝置層的多層膜於一側的主面,該多層膜的等方性膜應力使該矽晶圓彎曲成碗型,其中面方位是(111)。
Description
本發明係有關於形成半導體裝置的基板材料之矽晶圓,且特別有關於做為3維NAND快閃記憶體(以下稱為「3DNAND」)等的高積層型半導體裝置的基板材料,合適的矽晶圓及其加工方法。
最近,3DNAND受到注目。3DNAND是將記憶體陣列在縱方向上積層化的NAND記憶體,將積層數(字元線的層數)設定為例如64層的話,每個單一晶粒能夠實現512Gbit(64GB)這樣非常大的記憶容量。又,不像習知的平面型NAND記憶體那樣提高平面方向的密度,而提高高度方向的密度,能夠提供不但大容量化而且寫入速度提昇或者省電化優秀的高性能的快閃記憶體。
半導體裝置的製造中,為了形成裝置構造而在矽晶圓上層積氧化膜、氮化膜、金屬膜等的各式各樣的材料的膜。這種積層膜會因為膜的性質與製程步驟的條件而有不同的膜應力,因為積層膜的膜應力,矽晶圓會產生彎曲。特別是,3DNAND中會將各個記憶體元件垂直地堆疊數十個以上,伴隨而來地積層膜的數目也幾何地增加,因此成比例地膜應力也會大幅增加,矽晶圓的彎曲也大幅增加。裝置製程步驟中矽晶圓大幅地彎曲,會產生成膜、加工、檢查等的後續步驟中的處理無法進行等的異常狀況。
有關具有3層以上的配線層的半導體裝置的製造,例如專利文獻1揭露了不受到製造裝置影響且不使用特殊層間膜的步驟,而能夠將矽基板的彎曲抑制到既定值以下的半導體裝置的製造方法。這個製造方法中,假設矽基板的厚度為T(μm)、直徑為D(吋)、配線層數為n,使用厚度滿足T≧62.4×D×[1.6(n-1)+1.0]1/2
的矽基板來製造半導體裝置。
又,專利文獻2、3揭露一種製造方法,在中央部凹入成碗狀的彎曲的磊晶成長用的矽晶圓表面上形成磊晶層,藉此製造平坦度高的磊晶矽晶圓。 先行技術文獻 專利文獻
專利文獻1:日本特開平9-266206號公報 專利文獻2:日本特開2008-140856號公報 專利文獻3:日本特開2010-34461號公報
然而,專利文獻1記載的半導體裝置的製造方法是以配線層的膜應力不變動為前提而無視於對製造步驟的依賴性。實際上因為膜應力會因應步驟條件而變動,所以不能夠單純地用配線層數來評價彎曲量,這個技術難以應用。又,12吋矽晶圓中配線層數為500層的情況下,根據上述計算式,矽晶圓的厚度滿足T≧777.1μm即可,但是這與12吋矽晶圓的標準厚度775μm幾乎相同,明顯地無法預期會有抑制彎曲的效果。
又,專利文獻2、3記載的技術為了減低磊晶成長後的晶圓的彎曲而預先形成具有彎曲的初期晶圓,這個方法並非在裝置製造步驟中減低晶圓的彎曲。也就是說,即使像這樣在磊晶晶圓上形成半導體裝置層使得晶圓彎曲,也無法減低磊晶晶圓本身的彎曲。又,即使將磊晶成長步驟看作是裝置步驟的一部分,如何計算針對想要減低的彎曲量而做出的形狀的彎曲量的方法也不明。又,該方法只能用於晶圓彎曲成碗狀的情況下,不適用於彎曲成鞍狀的晶圓的情況。
矽晶圓的厚度、形狀、結晶方位等的規格在事前與彎曲量或彎曲形狀無關地被制定。因此,即使裝置製造步驟中產生矽晶圓的彎曲,也沒有矽晶圓的規格變更的基準,而無法應對晶圓的彎曲。
因此,本發明的目的是提供一種矽晶圓及其加工方法,能夠減低3DNAND等的半導體裝置的製造步驟中產生的晶圓彎曲,沒有問題地實施因為晶圓大幅彎曲而會產生異常的後續步驟。
為了解決上述問題,本發明的矽晶圓,在裝置製造步驟中形成構成半導體裝置層的多層膜於一側的主面,該多層膜的等方性膜應力使該矽晶圓彎曲成碗型,其中面方位是(111)。
在裝置製造步驟中,晶圓彎曲成碗型的情況下,使用彎曲的方位依存性小(111)的矽晶圓,能夠提高抑制碗型彎曲的效果。因此,能夠提供一種矽晶圓,能夠沒有問題地實施因為晶圓大幅彎曲而會產生異常的後續步驟。
本發明的矽晶圓中,氧濃度是8.0×1017
atoms/cm3
以上(ASTM F121, 1979)為佳。藉由提高結晶中的氧濃度使矽晶圓的楊氏模數上升,因此能夠提高彎曲抑制效果。
本發明中,該半導體裝置層包括3DNAND快閃記憶體為佳。如上述,3DNAND快閃記憶體因為記憶胞陣列的積層數非常多而造成晶圓的彎曲問題顯著。也就是說,隨著裝置製造步驟的進行而增加積層數時,晶圓的彎曲也逐漸增加,產生了到達最上層前晶圓的彎曲量超過容許範圍使得無法進行之後的裝置製造步驟的情況。然而,根據本發明,從形成裝置之前的晶圓階段就考量抑制晶圓的彎曲的對策,藉此能夠改善彎曲的問題,能夠迴避裝置製造步驟無法繼續進行的狀況。
又,本發明的矽晶圓,在裝置製造步驟中形成構成半導體裝置層的多層膜於一側的主面,該多層膜的異方性膜應力使該矽晶圓彎曲成鞍型,其中面方位是(110),缺口方位是<111>。
在裝置製造步驟中,晶圓彎曲成鞍型的情況下,使用彎曲的方位依存性大的面方位為(110)且缺方位是<111>的矽晶圓,藉此能夠使晶圓的彎曲變大的方向與結晶方位的楊氏模數大的方向一致,能夠提高抑制鞍型彎曲的效果。因此,能夠提供一種矽晶圓,能夠沒有問題地實施因為晶圓大幅彎曲而會產生異常的後續步驟。
本發明的矽晶圓中,氧濃度是6×1017
atoms/cm3
以上(ASTM F121, 1979)為佳。藉由提高結晶中的氧濃度使矽晶圓的楊氏模數上升,因此能夠提高彎曲抑制效果。
本發明中,該半導體裝置層包括3DNAND快閃記憶體為佳。如上述,3DNAND快閃記憶體因為記憶胞陣列的積層數非常多而造成晶圓的彎曲問題顯著。也就是說,隨著裝置製造步驟的進行而增加積層數時,晶圓的彎曲也逐漸增加,產生了到達最上層前晶圓的彎曲量超過容許範圍使得無法進行之後的裝置製造步驟的情況。然而,根據本發明,從形成裝置之前的晶圓階段就考量抑制晶圓的彎曲的對策,藉此能夠改善彎曲的問題,能夠迴避裝置製造步驟無法繼續進行的狀況。
本發明的矽晶圓的加工方法係準備了面方位是(111)的矽晶圓,在該矽晶圓的一側的主面形成構成半導體裝置層的多層膜,且抑制因為該多層膜的等方性的膜應力所產生的碗型的彎曲。根據本發明,能夠抑制裝置製造步驟中因為膜應力所產生的晶圓的彎曲。
又,本發明的矽晶圓的加工方法係準備了面方位是(110)且缺口方位是<111>的矽晶圓,在該矽晶圓的一側的主面形成構成半導體裝置層的多層膜,且將因為該多層膜的異方性的膜應力所產生的鞍型的彎曲的朝向配合該缺口方位,來抑制該鞍型的彎曲。根據本發明,能夠抑制裝置製造步驟中因為膜應力所產生的晶圓的彎曲。
根據本發明,能夠提供一種矽晶圓的製造方法,能夠減低裝置的製造步驟中產生的晶圓彎曲,沒有問題地實施因為晶圓大幅彎曲而會產生異常的後續步驟。
以下,一邊參照圖式,一邊詳細說明本發明較佳的實施型態。
第1圖係顯示本發明的第1實施型態的矽晶圓的構造的略平面圖。
如第1圖所示,這個矽晶圓1A在裝置製造步驟中在一側的主面形成有構成3DNAND快閃記憶體等的半導體裝置層的多層膜,多層膜形成的等方性膜應力將高積層型半導體裝置用矽晶圓彎曲成碗型,面方位是(111),缺口方位是<110>或<112>。也就是說,缺口2形成於<110>或<112>方向。
矽晶圓1A的氧濃度在8.0×1017
atoms/cm3
以上(ASTM F121, 1979)為佳。(111)矽晶圓的楊氏模量具有氧濃度依賴性,能夠提高當氧濃度在8.0×1017
atoms/cm3
以上的時候的彎曲抑制效果。
第2圖係顯示本發明的第2實施型態的矽晶圓的構造的略平面圖。
如第2圖所示,這個矽晶圓1B在裝置製造步驟中在一側的主面形成有構成半導體裝置層的多層膜,多層膜形成的異方性膜應力將高積層型半導體裝置用矽晶圓彎曲成鞍型,面方位是(110),缺口方位是<111>。也就是說,缺口2形成於<111>方向。
矽晶圓1B的氧濃度在6.0×1017
atoms/cm3
以上(ASTM F121, 1979)為佳。(110)矽晶圓的楊氏模量具有氧濃度依賴性,能夠提高當氧濃度在6.0×1017
atoms/cm3
以上的時候的彎曲抑制效果。
第3圖係用以說明施加膜應力至平坦的矽晶圓時產生的彎曲的種類的概要圖,(a)是碗狀彎曲,(b)是鞍狀彎曲。
矽晶圓的彎曲方式有碗型與鞍型2種。施加膜應力給平坦的矽晶圓時,有等方性的膜應力的話,如第3(a)圖所示地產生碗型的彎曲,有異方性的膜應力的話,如第3(b)圖所示地產生鞍型的彎曲。在此,碗型是指晶圓的外周部全周比中央部更往上方或下方移位的形狀。又,鞍型是指晶圓的X方向及Y方向中的任一者的兩端部比中央部更往上方(或下方)移位,鞍型是指晶圓的X方向及Y方向中的另一者的兩端部比中央部更往下方(或上方)移位的形狀。
碗型是指晶圓的外周部全周比中央部更往上方或下方移位的形狀。又,鞍型是指晶圓的X方向及Y方向中的任一者的兩端部比中央部更往上方(或下方)移位,鞍型是指晶圓的X方向及Y方向中的另一者的兩端部比中央部更往下方(或上方)移位的形狀。
第4圖係用以說明施加到矽晶圓的膜應力造成的晶圓的彎曲方式的差異的概要圖。
如第4圖所示,在矽晶圓的表面形成構成半導體裝置的配線層等的積層膜時,該矽晶圓上會產生膜應力,因此如(a)所示地產生碗型彎曲,或者是如(b)所示地產生鞍型彎曲。這種晶圓的彎曲變大的話後續步驟中會發生各式各樣的問題。
裝置製造步驟中,矽晶圓彎曲成鞍型的理由是因為形成在矽晶圓上的膜的膜應力的符號不同而產生膜應力的異方性。例如,如第4圖所示,X方向的壓縮應力所支配的配線層,再加上與X方向垂直的Y方向上有拉伸應力的配線層成膜時,X方向的壓縮應力被強調,矽晶圓彎曲成鞍型。
矽結晶的楊氏模數會因為結晶方位而不同,具有方位依賴性。在[100]方向上是130MPa,在[110]方向上是170MPa,在[111]方向上是189MPa,楊氏模數較小者容易發生變形。晶圓彎曲成鞍型的情況下,彎曲最大的方向與結晶方位的楊氏模數小的方向一致的話,會更容易彎曲,彎曲量會增加。相反地,彎曲最大的方向與結晶方位的楊氏模數大的方向一致的話,會更難彎曲,彎曲量減少。
因此,本實施型態中,裝置製造步驟中晶圓彎曲成鞍型的情況下,會使用彎曲的方位依存性大的面方位是(110),且缺口方位是<111>的矽晶圓1B(參照第2圖)。通常,裝置製造步驟中會配合缺口方位來形成半導體裝置,因此將配向層的朝向配合缺口方位,能夠使晶圓的彎曲變大的方向與結晶方位的楊氏模數大的方向一致,能夠提高抑制鞍型的彎曲的效果。
又,裝置製造步驟中晶圓彎曲成碗型的情況下,會使用沒有彎曲的方位依存性的面方向是(111)的矽晶圓1A(參照第1圖),配合在裝置製造步驟中被給予的等方性的膜應力使矽晶圓的楊氏模數也是等方性,藉此能夠提高抑制碗型的彎曲的效果。
以上,說明了本發明較佳的實施型態,但本發明並不限定於上述的實施型態,在不脫離本發明的主旨的範圍內能夠做各式各樣的變更,這些變更當然也包含於本發明的範圍內。
例如,上述實施型態中,雖然說明了適合3DNAND的製造的矽晶圓的製造方法,但本發明並不限定於這樣的例子,能夠以因為膜應力而造成晶圓彎曲的各式各樣的半導體裝置中的矽晶圓為對象。 (實施例1)
準備面方位及缺口方位不同的矽晶圓的樣本#1~#16。各晶圓是以CZ法生成,直徑為300mm,厚度為775μm。晶圓樣本的面方位是(100)、(110)、(111)3個種類,面方位(100)晶圓的缺口方位是<110>與<100>2種類,面方位(110)晶圓的缺口方位是<110>與<111>2種類,面方位(111)晶圓的缺口方位是<110>與<112>2種類。使用的晶圓的面方位及缺口方位的不一致會在±1度以內。
接著,測量各個晶圓的氧濃度。氧濃度全部都是ASTM F121, 1979所規定的傅立葉轉換紅外線分光光度法(FT-IR)的測量值。
接著,這些晶圓樣本#1~#16的主面以CVD步驟形成厚度2μm的矽氧化膜時,產生了凸狀的碗型彎曲。各晶圓的彎曲量(WARP)的測量結果顯示於表1。
從表1可知,面方位(100)的晶圓樣本#1~#4中,不管基板氧濃度或缺口方位,都會發生600μm左右的大小的彎曲。
面方位(110)的晶圓樣本#5~#8中,不管基板氧濃度、缺口方位,都會770μm左右的大小的彎曲。氧濃度越高彎曲量越減少,但沒有太大的差。
面方位(111)的晶圓樣本#9~#16中,可知不管缺口方位,比面方位(100)或(110)的晶圓更能夠抑制彎曲量。又,晶圓的彎曲有氧濃度依賴性,氧濃度在8.0×1017
atoms/cm3
以上時的彎曲抑制效果特別地高。這是藉由氧濃度增高使得矽結晶的楊氏模數上升的效果。
矽晶圓的楊氏模數因為結晶方位而有不同的方位依存性,因此給予碗型的彎曲這種異方性少的膜應力時,會因為面方位的不同使得相對於彈性變形的耐性變化。從以上的結果可知,使用(111)晶圓能夠抑制裝置製造步驟中會形成問題的彎曲。 (實施例2)
與實施例1相同地,準備面方位及缺口方位不同的矽晶圓的樣本#17~#31,測量這些晶圓的氧濃度。
接著,在這些晶圓樣本#17~#31的主面以CVD步驟形成厚度1μm的氧化矽膜後,使用光罩進行一部分蝕刻,接著以CVD步驟形成厚度0.7μm的氮化矽膜後,使用光罩進行一部分蝕刻,製作如第5圖所示的形狀的膜。例如樣本#17的(100)晶圓情況下,氧化矽膜是<110>方位上細長的矩形圖樣,氮化矽膜是與氧化矽膜的長方向垂直的方向上細長的矩形圖樣,藉由這些合成圖樣,矽晶圓上產生異方性的膜應力,產生了鞍型彎曲。各晶圓的彎曲量(WARP)的測量結果顯示於表2。
從表2可知,面方位(100)的晶圓樣本#17~#20中,基板氧濃度或缺口方位會造成彎曲量變化,特別是<111>缺口比<100>缺口的彎曲抑制效果高。然而,(100)晶圓的<110>缺口是晶圓的標準方位。
面方位(110)的晶圓樣本#21~#27中,基板氧濃度或缺口方位會造成彎曲量變化,特別是<111>缺口的彎曲抑制效果高。又,即使是<111>缺口的晶圓樣本#24~#27中,氧濃度在6×1017
atoms/cm3
以上的樣本#25、#26、#27的彎曲抑制效果特高。
面方位(111)的晶圓樣本#28~#31中,不管基板氧濃度或缺口方位,都會產生500μm左右的大的彎曲。然而,(111)晶圓的<110>缺口是晶圓的標準方位。
1A、1B‧‧‧矽晶圓2‧‧‧缺口
第1圖係顯示本發明的第1實施型態的矽晶圓的構造的略平面圖。 第2圖係顯示本發明的第2實施型態的矽晶圓的構造的略平面圖。 第3圖係用以說明施加膜應力至平坦的矽晶圓時產生的彎曲的種類的概要圖,(a)是碗狀彎曲,(b)是鞍狀彎曲。 第4圖係用以說明施加到矽晶圓的膜應力造成的晶圓的彎曲方式的差異的概要圖。 第5圖係顯示對矽晶圓施加異方性的膜應力之成膜圖樣之一例的略立體圖。
1A‧‧‧矽晶圓
Claims (3)
- 一種矽晶圓,在裝置製造步驟中形成構成半導體裝置層的多層膜於一側的主面,該多層膜的異方性膜應力使該矽晶圓彎曲成鞍型,其中面方位是(110),缺口方位是<111>。
- 如申請專利範圍第1項所述之矽晶圓,其中氧濃度是6×1017atoms/cm3以上(ASTM F121,1979)。
- 如申請專利範圍第1或2項所述之矽晶圓,其中該半導體裝置層包括3DNAND快閃記憶體。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017134918A JP6834816B2 (ja) | 2017-07-10 | 2017-07-10 | シリコンウェーハの加工方法 |
JP2017-134918 | 2017-07-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201909391A TW201909391A (zh) | 2019-03-01 |
TWI682524B true TWI682524B (zh) | 2020-01-11 |
Family
ID=65001991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107120956A TWI682524B (zh) | 2017-07-10 | 2018-06-19 | 矽晶圓 |
Country Status (6)
Country | Link |
---|---|
US (2) | US20200176461A1 (zh) |
JP (1) | JP6834816B2 (zh) |
KR (1) | KR102331580B1 (zh) |
CN (1) | CN111164240B (zh) |
TW (1) | TWI682524B (zh) |
WO (1) | WO2019012867A1 (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0529324A (ja) * | 1991-07-22 | 1993-02-05 | Mitsubishi Materials Corp | シリコンウエーハの製造方法 |
US20080132032A1 (en) * | 2006-11-30 | 2008-06-05 | Shinichi Tomita | Method for manufacturing silicon wafer |
TW201025453A (en) * | 2008-12-26 | 2010-07-01 | Siltronic Ag | Silicon wafer and method of manufacturing the same |
US20140374771A1 (en) * | 2012-03-16 | 2014-12-25 | Furukawa Electric Co., Ltd. | Semiconductor multi-layer substrate, semiconductor device, and method for manufacturing the same |
TWI550143B (zh) * | 2014-02-26 | 2016-09-21 | Sumco Corp | Production method of epitaxial silicon wafer and epitaxial silicon wafer |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09266206A (ja) | 1996-03-28 | 1997-10-07 | Nec Corp | 半導体装置の製造方法およびシリコン基板 |
JPH1032233A (ja) * | 1996-07-15 | 1998-02-03 | Seiko Epson Corp | シリコンウェーハ、ガラスウェーハ及びそれを用いたストレス測定方法 |
CN100403543C (zh) | 2001-12-04 | 2008-07-16 | 信越半导体株式会社 | 贴合晶片及贴合晶片的制造方法 |
US7262112B2 (en) | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
JP5250968B2 (ja) | 2006-11-30 | 2013-07-31 | 株式会社Sumco | エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。 |
US7816765B2 (en) * | 2008-06-05 | 2010-10-19 | Sumco Corporation | Silicon epitaxial wafer and the production method thereof |
JP5625229B2 (ja) | 2008-07-31 | 2014-11-19 | 株式会社Sumco | エピタキシャルシリコンウェーハおよびその製造方法 |
US8084822B2 (en) * | 2009-09-30 | 2011-12-27 | International Business Machines Corporation | Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices |
CN102208337B (zh) * | 2010-03-30 | 2014-04-09 | 杭州海鲸光电科技有限公司 | 一种硅基复合衬底及其制造方法 |
DE102010034002B4 (de) * | 2010-08-11 | 2013-02-21 | Siltronic Ag | Siliciumscheibe und Verfahren zu deren Herstellung |
US20120064682A1 (en) * | 2010-09-14 | 2012-03-15 | Jang Kyung-Tae | Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices |
US8625083B2 (en) * | 2011-03-12 | 2014-01-07 | Ken Roberts | Thin film stress measurement 3D anisotropic volume |
CN102354664B (zh) * | 2011-09-28 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | 金属间介质层形成方法及半导体器件 |
JP6277677B2 (ja) * | 2013-11-01 | 2018-02-14 | 大日本印刷株式会社 | エッチングマスクの設計方法、構造体の製造方法及びエッチングマスク |
US9490116B2 (en) * | 2015-01-09 | 2016-11-08 | Applied Materials, Inc. | Gate stack materials for semiconductor applications for lithographic overlay improvement |
CN105448666A (zh) * | 2015-12-02 | 2016-03-30 | 苏州工业园区纳米产业技术研究院有限公司 | 利用二氧化硅的应力来改变晶圆硅片基体弯曲度的方法 |
-
2017
- 2017-07-10 JP JP2017134918A patent/JP6834816B2/ja active Active
-
2018
- 2018-06-06 CN CN201880046219.1A patent/CN111164240B/zh active Active
- 2018-06-06 WO PCT/JP2018/021721 patent/WO2019012867A1/ja active Application Filing
- 2018-06-06 KR KR1020197035098A patent/KR102331580B1/ko active IP Right Grant
- 2018-06-06 US US16/619,143 patent/US20200176461A1/en not_active Abandoned
- 2018-06-19 TW TW107120956A patent/TWI682524B/zh active
-
2021
- 2021-12-03 US US17/541,767 patent/US12004344B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0529324A (ja) * | 1991-07-22 | 1993-02-05 | Mitsubishi Materials Corp | シリコンウエーハの製造方法 |
US20080132032A1 (en) * | 2006-11-30 | 2008-06-05 | Shinichi Tomita | Method for manufacturing silicon wafer |
TW201025453A (en) * | 2008-12-26 | 2010-07-01 | Siltronic Ag | Silicon wafer and method of manufacturing the same |
US20140374771A1 (en) * | 2012-03-16 | 2014-12-25 | Furukawa Electric Co., Ltd. | Semiconductor multi-layer substrate, semiconductor device, and method for manufacturing the same |
TWI550143B (zh) * | 2014-02-26 | 2016-09-21 | Sumco Corp | Production method of epitaxial silicon wafer and epitaxial silicon wafer |
Also Published As
Publication number | Publication date |
---|---|
CN111164240A (zh) | 2020-05-15 |
US20200176461A1 (en) | 2020-06-04 |
JP2019014638A (ja) | 2019-01-31 |
US12004344B2 (en) | 2024-06-04 |
WO2019012867A1 (ja) | 2019-01-17 |
KR102331580B1 (ko) | 2021-11-25 |
KR20190142388A (ko) | 2019-12-26 |
TW201909391A (zh) | 2019-03-01 |
JP6834816B2 (ja) | 2021-02-24 |
CN111164240B (zh) | 2021-12-28 |
US20220093624A1 (en) | 2022-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI682526B (zh) | 矽晶圓的製造方法 | |
JP6777029B2 (ja) | シリコンウェーハ及びその製造方法 | |
JP7025589B2 (ja) | ウェーハ平坦性を改善する方法およびその方法により作成された接合ウェーハ組立体 | |
WO2013046525A1 (ja) | 貼り合わせsoiウェーハの反りを算出する方法、及び貼り合わせsoiウェーハの製造方法 | |
TWI645454B (zh) | 磊晶基板及其製造方法 | |
TWI682524B (zh) | 矽晶圓 | |
JP2009111423A5 (ja) | GaN結晶基板およびその製造方法 | |
TW201933301A (zh) | 可撓性顯示器及其製造方法 | |
KR102352511B1 (ko) | 실리콘에피택셜 웨이퍼의 제조방법 및 반도체 디바이스의 제조방법 | |
KR102622608B1 (ko) | 패키징 기판 및 이의 제조방법 | |
TWI588085B (zh) | 微奈米化晶片及其製造方法 | |
US20100081233A1 (en) | Method of manufacturing integrated circuit having stacked structure and the integrated circuit | |
TW201423984A (zh) | 異質接面半導體複合薄膜及其製造方法 |