JP6834816B2 - シリコンウェーハの加工方法 - Google Patents
シリコンウェーハの加工方法 Download PDFInfo
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- JP6834816B2 JP6834816B2 JP2017134918A JP2017134918A JP6834816B2 JP 6834816 B2 JP6834816 B2 JP 6834816B2 JP 2017134918 A JP2017134918 A JP 2017134918A JP 2017134918 A JP2017134918 A JP 2017134918A JP 6834816 B2 JP6834816 B2 JP 6834816B2
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- 229910052710 silicon Inorganic materials 0.000 title claims description 86
- 239000010703 silicon Substances 0.000 title claims description 86
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 84
- 238000003672 processing method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 56
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 15
- 235000012431 wafers Nutrition 0.000 description 140
- 239000010410 layer Substances 0.000 description 26
- 230000000694 effects Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02027—Setting crystal orientation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mechanical Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Formation Of Insulating Films (AREA)
Description
T≧62.4×D×[1.6(n-1)+1.0]1/2
を満足する厚さを満足するシリコン基板を用いて半導体装置を製造する。
面方位及びノッチ方位が異なるシリコンウェーハのサンプル#1〜#16を用意した。各ウェーハはCZ法で育成されたものであり、直径は300mm、厚みは775μmである。ウェーハサンプルの面方位は(100)、(110)、(111)の3種類であり、面方位(100)ウェーハのノッチ方位は<110>と<100>の2種類、面方位(110)ウェーハのノッチ方位は<110>と<111>の2種類、面方位(111)ウェーハのノッチ方位は<110>と<112>の2種類である。使用したウェーハの面方位及びノッチ方位のばらつきは±1度以内である。
実施例1と同様に面方位及びノッチ方位が異なるシリコンウェーハのサンプル#17〜#31を用意し、それらのウェーハの酸素濃度を測定した。
2 ノッチ
Claims (4)
- シリコンウェーハの一方の主面に半導体デバイス層を構成する多層膜を形成するシリコンウェーハの加工方法であって、
デバイス工程中に前記多層膜の等方性の膜応力によってシリコンウェーハがお椀型に反る場合に、面方位が(111)のシリコンウェーハを使用して前記多層膜を形成し、
デバイス工程中に前記多層膜の異方性の膜応力によってシリコンウェーハが鞍型に反る場合に、面方位が(110)でノッチ方位が<111>のシリコンウェーハを使用すると共に、前記シリコンウェーハの反りが大きくなる方向と結晶方位のヤング率が大きい方向が一致するように前記多層膜を形成することを特徴とするシリコンウェーハの加工方法。 - 面方位が(111)のシリコンウェーハの酸素濃度が8.0×1017atoms/cm3以上(ASTM F121,1979)である、請求項1に記載のシリコンウェーハの加工方法。
- 面方位が(110)でノッチ方位が<111>のシリコンウェーハの酸素濃度が6.0×1017atoms/cm3以上(ASTM F121,1979)である、請求項1に記載のシリコンウェーハの加工方法。
- 前記半導体デバイス層は3DNANDフラッシュメモリを含む、請求項1乃至3のいずれか一項に記載のシリコンウェーハの加工方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017134918A JP6834816B2 (ja) | 2017-07-10 | 2017-07-10 | シリコンウェーハの加工方法 |
CN201880046219.1A CN111164240B (zh) | 2017-07-10 | 2018-06-06 | 硅晶片 |
KR1020197035098A KR102331580B1 (ko) | 2017-07-10 | 2018-06-06 | 실리콘 웨이퍼 |
US16/619,143 US20200176461A1 (en) | 2017-07-10 | 2018-06-06 | Silicon wafer |
PCT/JP2018/021721 WO2019012867A1 (ja) | 2017-07-10 | 2018-06-06 | シリコンウェーハ |
TW107120956A TWI682524B (zh) | 2017-07-10 | 2018-06-19 | 矽晶圓 |
US17/541,767 US12004344B2 (en) | 2017-07-10 | 2021-12-03 | Method of reducing wrap imparted to silicon wafer by semiconductor layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017134918A JP6834816B2 (ja) | 2017-07-10 | 2017-07-10 | シリコンウェーハの加工方法 |
Publications (2)
Publication Number | Publication Date |
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JP2019014638A JP2019014638A (ja) | 2019-01-31 |
JP6834816B2 true JP6834816B2 (ja) | 2021-02-24 |
Family
ID=65001991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2017134918A Active JP6834816B2 (ja) | 2017-07-10 | 2017-07-10 | シリコンウェーハの加工方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20200176461A1 (ja) |
JP (1) | JP6834816B2 (ja) |
KR (1) | KR102331580B1 (ja) |
CN (1) | CN111164240B (ja) |
TW (1) | TWI682524B (ja) |
WO (1) | WO2019012867A1 (ja) |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0529324A (ja) * | 1991-07-22 | 1993-02-05 | Mitsubishi Materials Corp | シリコンウエーハの製造方法 |
JPH09266206A (ja) | 1996-03-28 | 1997-10-07 | Nec Corp | 半導体装置の製造方法およびシリコン基板 |
JPH1032233A (ja) * | 1996-07-15 | 1998-02-03 | Seiko Epson Corp | シリコンウェーハ、ガラスウェーハ及びそれを用いたストレス測定方法 |
CN100403543C (zh) * | 2001-12-04 | 2008-07-16 | 信越半导体株式会社 | 贴合晶片及贴合晶片的制造方法 |
US7262112B2 (en) * | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
JP5250968B2 (ja) | 2006-11-30 | 2013-07-31 | 株式会社Sumco | エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。 |
US7902039B2 (en) * | 2006-11-30 | 2011-03-08 | Sumco Corporation | Method for manufacturing silicon wafer |
US7816765B2 (en) * | 2008-06-05 | 2010-10-19 | Sumco Corporation | Silicon epitaxial wafer and the production method thereof |
JP5625229B2 (ja) | 2008-07-31 | 2014-11-19 | 株式会社Sumco | エピタキシャルシリコンウェーハおよびその製造方法 |
JP5537802B2 (ja) * | 2008-12-26 | 2014-07-02 | ジルトロニック アクチエンゲゼルシャフト | シリコンウエハの製造方法 |
CN102208337B (zh) * | 2010-03-30 | 2014-04-09 | 杭州海鲸光电科技有限公司 | 一种硅基复合衬底及其制造方法 |
DE102010034002B4 (de) * | 2010-08-11 | 2013-02-21 | Siltronic Ag | Siliciumscheibe und Verfahren zu deren Herstellung |
US8625083B2 (en) * | 2011-03-12 | 2014-01-07 | Ken Roberts | Thin film stress measurement 3D anisotropic volume |
CN102354664B (zh) * | 2011-09-28 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | 金属间介质层形成方法及半导体器件 |
WO2013137476A1 (ja) * | 2012-03-16 | 2013-09-19 | 次世代パワーデバイス技術研究組合 | 半導体積層基板、半導体素子、およびその製造方法 |
JP6277677B2 (ja) * | 2013-11-01 | 2018-02-14 | 大日本印刷株式会社 | エッチングマスクの設計方法、構造体の製造方法及びエッチングマスク |
JP6156188B2 (ja) * | 2014-02-26 | 2017-07-05 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
CN105448666A (zh) * | 2015-12-02 | 2016-03-30 | 苏州工业园区纳米产业技术研究院有限公司 | 利用二氧化硅的应力来改变晶圆硅片基体弯曲度的方法 |
-
2017
- 2017-07-10 JP JP2017134918A patent/JP6834816B2/ja active Active
-
2018
- 2018-06-06 WO PCT/JP2018/021721 patent/WO2019012867A1/ja active Application Filing
- 2018-06-06 KR KR1020197035098A patent/KR102331580B1/ko active IP Right Grant
- 2018-06-06 US US16/619,143 patent/US20200176461A1/en not_active Abandoned
- 2018-06-06 CN CN201880046219.1A patent/CN111164240B/zh active Active
- 2018-06-19 TW TW107120956A patent/TWI682524B/zh active
Also Published As
Publication number | Publication date |
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TWI682524B (zh) | 2020-01-11 |
KR20190142388A (ko) | 2019-12-26 |
CN111164240A (zh) | 2020-05-15 |
CN111164240B (zh) | 2021-12-28 |
US20220093624A1 (en) | 2022-03-24 |
JP2019014638A (ja) | 2019-01-31 |
US20200176461A1 (en) | 2020-06-04 |
TW201909391A (zh) | 2019-03-01 |
KR102331580B1 (ko) | 2021-11-25 |
WO2019012867A1 (ja) | 2019-01-17 |
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