CN114556529A - 半导体晶片及其制造方法 - Google Patents
半导体晶片及其制造方法 Download PDFInfo
- Publication number
- CN114556529A CN114556529A CN201980101276.XA CN201980101276A CN114556529A CN 114556529 A CN114556529 A CN 114556529A CN 201980101276 A CN201980101276 A CN 201980101276A CN 114556529 A CN114556529 A CN 114556529A
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- semiconductor wafer
- insulating film
- small blocks
- gallium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 122
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 114
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 114
- 239000010703 silicon Substances 0.000 claims abstract description 114
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 72
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/042—Coating on selected surface areas, e.g. using masks using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C23C16/303—Nitrides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
- C30B23/04—Pattern deposit, e.g. by using masks
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/04—Pattern deposit, e.g. by using masks
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/38—Nitrides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mechanical Engineering (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
本申请的发明所涉及的半导体晶片的制造方法具备:第一工序,在硅基板的上表面形成被分割成多个小区块的氮化镓生长层;和第二工序,用绝缘膜填埋多个小区块之间,绝缘膜对硅基板施加与氮化镓生长层对硅基板施加的应力相反方向的应力。
Description
技术领域
本发明涉及半导体晶片及其制造方法。
背景技术
在专利文献1中公开了在蓝宝石或碳化硅基板上使具有与基板不同的晶格常数的半导体层生长的方法。在该方法中,在基板上的规定部位形成具有用于使半导体层选择性地生长的开口部的层,并通过开口部使基板的规定部位露出。接下来,在通过开口部而露出的基板的表面上选择性地使半导体层异质外延生长。
专利文献1:日本特开平10-135140号公报
当在硅基板生长氮化镓时,存在因两者的晶格常数之差引起基板翘曲的情况。在专利文献1的方法中,通过分割半导体层,能够减少基板翘曲。然而,在专利文献1的方法中,有可能无法充分地抑制翘曲。由此,曝光工序等之后的工序有可能变得困难。
发明内容
本发明是为了解决上述问题而做出的,其目的在于得到一种能够抑制基板的翘曲的半导体晶片及其制造方法。
本申请的发明所涉及的半导体晶片的制造方法具备:第一工序,在硅基板的上表面形成被分割成多个小区块的氮化镓生长层;和第二工序,用绝缘膜填埋该多个小区块之间,该绝缘膜对该硅基板施加与该氮化镓生长层对该硅基板施加的应力相反方向的应力。
本申请的发明所涉及的半导体晶片具备:硅基板;氮化镓生长层,设置于该硅基板的上表面,并被分割成多个小区块;以及绝缘层,设置于该硅基板的上表面,并填埋该多个小区块之间,该绝缘层对该硅基板施加与该氮化镓生长层对该硅基板施加的应力相反方向的应力。
在本申请的发明所涉及的半导体晶片的制造方法中,通过绝缘膜能够抑制硅基板的翘曲。
在本申请的发明所涉及的半导体晶片中,通过绝缘层能够抑制硅基板的翘曲。
附图说明
图1是实施方式1所涉及的半导体晶片的剖视图。
图2是表示在硅基板形成有热氧化膜的状态的俯视图。
图3是表示去除了热氧化膜的状态的俯视图。
图4是表示去除了热氧化膜的状态的剖视图。
图5是表示形成有绝缘膜的状态的剖视图。
图6是实施方式2所涉及的半导体晶片的剖视图。
图7是说明实施方式2所涉及的半导体晶片的制造方法的剖视图。
图8是表示使多个小区块的上表面露出的状态的剖视图。
图9是实施方式3所涉及的半导体晶片的剖视图。
图10是实施方式4所涉及的半导体晶片的剖视图。
具体实施方式
参照附图对本发明的实施方式所涉及的半导体晶片及其制造方法进行说明。有时对相同的或对应的构成要素标注相同的附图标记,省略重复说明。
实施方式1
图1是实施方式1所涉及的半导体晶片100的剖视图。半导体晶片100具备硅基板10。在硅基板10的上表面设置有氮化镓生长层12。氮化镓生长层12被分割成多个小区块13。多个小区块13相互分离。氮化镓生长层例如为包含In1-x-yGaxAlyN层的多层膜。这里,0≤x≤1、0≤y≤1。
在硅基板10的上表面设置有绝缘膜14。绝缘膜14填埋多个小区块13之间。绝缘膜14的厚度例如为1μm以上,且为氮化镓生长层12的厚度以下。绝缘膜14例如为氮化硅膜。绝缘膜14从硅基板10的一端连接到另一端。
接下来,对半导体晶片100的制造方法进行说明。首先,在硅基板10的上表面形成热氧化膜16。图2是表示在硅基板10形成有热氧化膜16的状态的俯视图。在热氧化膜16通过光刻而形成格子状的图案。由此,形成格子状的氧化膜。硅基板10的上表面由热氧化膜16划分成多个区域11。
接下来,在硅基板10形成氮化镓生长层12。氮化镓生长层12例如通过有机金属气相生长法或分子束外延法形成。由此,在硅基板10中的未被热氧化膜16覆盖的部分形成氮化镓生长层12。即,在多个区域11分别生长多个小区块13。其中,氮化镓生长层12设为包含用于使氮化镓外延生长的缓冲层。
其后,去除热氧化膜16。在去除中例如使用氢氟酸。图3是表示去除了热氧化膜16的状态的俯视图。图4是表示去除了热氧化膜16的状态的剖视图。以上是在硅基板10的上表面形成被分割成多个小区块13的氮化镓生长层12的第一工序。
接下来,实施用绝缘膜14填埋多个小区块13之间的第二工序。图5是表示形成了绝缘膜14的状态的剖视图。绝缘膜14例如通过CVD(Chemical Vapor Deposition:化学气相沉积)法堆积于硅基板10之上。绝缘膜14形成为与硅基板10紧贴。
绝缘膜14对硅基板10施加与氮化镓生长层12对硅基板10施加的应力相反方向的应力。绝缘膜14由对硅基板10施加与氮化镓生长层12相反的应力的材料形成。绝缘膜14例如为氮化硅膜或氧化硅膜。优选为绝缘膜14由对硅基板10施加的应力大的材料形成。
通常,氮化硅膜根据成膜条件而能够产生数GPa左右的拉伸应力或压缩应力。虽然取决于制造装置,但在通过等离子体CVD形成的氮化硅膜中能够得到300MPa左右的膜应力,在通过热CVD形成的氮化硅膜中能够得到1GPa左右的膜应力。另外,绝缘膜14也可以通过ECR(Electron Cyclotron Resonance:电子回旋共振)溅射形成。在通过ECR溅射形成的氮化硅膜中,能够得到3GPa左右的膜应力。
例如也可以使用SiH4和NH3作为工艺气体,通过等离子体CVD形成绝缘膜14。在该情况下,通过使SiH4相对于NH3的比率在0.5~2之间变化,能够使膜应力变化至100MPa左右的拉伸应力~300MPa左右的压缩应力。因此,例如通过将SiH4相对于NH3的比率设定为0.5以下,能够从绝缘膜14向硅基板10施加拉伸应力。另外,通过将SiH4相对于NH3的比率设定为2以上,能够从绝缘膜14向硅基板10施加拉伸应力。
接下来,如图1所示,直到氮化镓生长层12露出为止去除绝缘膜14。绝缘膜14的去除通过干式蚀刻等蚀刻来进行。此时,通过调整蚀刻时间,来调整绝缘膜14的厚度。通常,绝缘膜14越厚,施加到硅基板10的应力越大。因此,通过调整蚀刻时间,能够调整绝缘膜14对硅基板10施加的应力的大小。
另外,与绝缘膜14的厚度成比例地能够矫正的翘曲变大。绝缘膜14的厚度也可以由形成有氮化镓生长层12且形成绝缘膜14之前的状态的硅基板10的翘曲量决定。绝缘膜14的厚度也可以设定为在形成有绝缘膜14的状态下硅基板10变得平坦。
通常,缓和基板的翘曲所需的绝缘膜的膜厚,取决于氮化镓生长层间的区域的大小或绝缘膜的膜应力的大小。例如,若以1μm的厚度堆积膜应力为1GPa的绝缘膜14,则与不设置绝缘膜14的情况相比,能够矫正数μm~10μm左右的硅基板10的翘曲。这里,将相邻的小区块13所夹的绝缘膜14的宽度相对于小区块13的宽度设定为1/10。另外,硅基板10的厚度设定为625μm。根据以上,通过例如将绝缘膜14的厚度设为1μm以上,能够充分地抑制硅基板10的翘曲。
根据以上,形成绝缘膜14。如图3所示,绝缘膜14形成在氮化镓生长层12被去除而硅基板10以格子状露出的部分。即,绝缘膜14形成为格子状。
接下来,在从绝缘膜14露出的氮化镓生长层12的表面形成电极等。由此,形成器件。
通常,通过使用氮化镓(GaN)、氮化镓铝(AlGaN)以及氮化铝(AlN)等基于氮化物的半导体材料,能够制作异质结构。因此,这些材料有时用于高频器件、光器件或功率器件的制造。
基于氮化物的半导体结构通常通过在碳化硅、蓝宝石或硅基板之上外延生长而制作。特别是硅基板比碳化硅等廉价。因此,能够降低材料成本。
这里,通常若在硅基板生长氮化镓则有时基板翘曲。由此,有时在搬运或曝光工序等工序中产生问题。
硅的晶格常数为0.5431nm。因此,在硅的(111)面上的原子间隔为0.5431/√2=0.3840nm。与此相对,氮化镓的晶格常数为0.3819nm。氮化镓的晶格间隔比硅窄。因此,硅基板从在(111)面上异质外延生长的氮化镓受压缩应力。
另外,硅的线膨胀系数为2.6×10-6K-1。与此相对,氮化镓的线膨胀系数为5.6×10-6K-1。通常,氮化镓在800℃以上的高温下生长。因此,在从生长温度降低至室温时,氮化镓收缩得比硅大。因此,硅基板从氮化镓生长层受压缩应力。
根据以上,若在硅基板形成氮化镓生长层,则以氮化镓生长层成为内侧的方式产生翘曲。实际上,翘曲的朝向根据外延生长的条件或缓冲层的构成而不同。
另外,可以想到通过将氮化镓生长层分割成小区块,分散应力,来减少基板翘曲的方法。但是,在这样的方法中,通常难以完全消除基板的翘曲。例如在4英寸基板中,有可能残留数μm~10μm左右的晶片翘曲。这样的翘曲特别是在需要形成微小图案的栅极曝光工序等中成为问题。
与此相对,本实施方式的绝缘膜14对硅基板10施加与氮化镓生长层12对硅基板10施加的应力相反方向的应力。即,在氮化镓生长层12对硅基板10施加压缩应力的情况下,使用对硅基板施加拉伸应力的膜作为绝缘膜14。另外,在氮化镓生长层12对硅基板10施加拉伸应力的情况下,使用对硅基板施加压缩应力的膜作为绝缘膜14。
由此,通过绝缘膜14能够抵消硅基板10从氮化镓生长层12受到的应力。因此,能够缓和硅基板10的翘曲。在本实施方式中,可得到将氮化镓生长层12分割成小区块13来分散应力的效果、和基于绝缘膜14实现的应力的抵消效果这两者。因此,能够抑制晶片的翘曲,容易地实施曝光工序。
另外,通过绝缘膜14的厚度,能够调节对硅基板10施加的应力。绝缘膜14的厚度能够通过蚀刻时间来调节。因此,能够容易地使硅基板10平坦。
此外,将图2所示的热氧化膜16形成得厚来抑制翘曲是困难的。在该情况下,在外延生长之前厚的热氧化膜16形成于硅基板10。此时,由于热氧化膜16的膜应力大,所以有可能在外延生长的开始时晶片成为大幅翘曲的状态。因此,外延生长工序有可能变得困难。
因此,热氧化膜16需要形成得薄以抑制硅基板10大幅翘曲。与此相对,绝缘膜14形成得比热氧化膜16厚以对硅基板10施加大的应力。
作为本实施方式的变形例,图3所示的去除氮化镓生长层12的区域并不局限于格子状。去除了氮化镓生长层12的区域只要能够将氮化镓生长层12分割成多个小区块13,也可以为其它形状。考虑到通过形成绝缘膜14来对硅基板10施加应力,去除了氮化镓生长层12的区域优选为在纵向和横向上从硅基板10的一端贯穿到另一端。
另外,第一工序也可以如下这样进行。首先,通过有机金属气相生长法或分子束外延法在硅基板10的整个上表面形成氮化镓生长层12。其后,在氮化镓生长层12之上形成光致抗蚀剂等掩模层。接下来,使用掩模层对氮化镓生长层12进行蚀刻直到硅基板10露出为止。由此,硅基板10以格子状露出,氮化镓生长层12被分割成多个小区块13。接下来,去除掩模层。
这些变形能够对以下实施方式所涉及的半导体晶片及其制造方法适当地应用。此外,对于以下实施方式所涉及的半导体晶片及其制造方法,由于与实施方式1的共通点多,因此围绕与实施方式1的不同点进行说明。
实施方式2
图6是实施方式2所涉及的半导体晶片200的剖视图。在半导体晶片200中,绝缘膜214的结构与半导体晶片100不同。在绝缘膜214且在多个小区块13中的相互相邻的一对小区块13之间形成有凹部215。
接下来,对半导体晶片200的制造方法进行说明。第一工序与实施方式相同。接下来,实施第二工序。图7是说明实施方式2所涉及的半导体晶片的制造方法的剖视图。首先,用绝缘膜214覆盖硅基板10的上表面、和多个小区块13的各个侧面以及上表面。
绝缘膜214沿着硅基板10和多个小区块13而形成。在绝缘膜214的表面形成有反映了多个小区块13的形状的凹凸。此时,在绝缘膜214中的相互相邻的一对小区块13之间的部分形成有凹部215。绝缘膜214中的覆盖小区块13的侧面的部分的厚度为,被相邻的小区块13夹住的区域的宽度的1/2以下。
接下来,涂敷抗蚀剂218。抗蚀剂218以填埋凹部215的方式设置于绝缘膜214之上。抗蚀剂218的上表面是平坦的。抗蚀剂218具有在抗蚀剂218的上表面不反映绝缘膜214的表面的凹凸的厚度。
接下来,实施蚀刻工序。由此使多个小区块13的上表面从绝缘膜214露出。图8是表示使多个小区块13的上表面露出的状态的剖视图。在蚀刻工序中,通过干式蚀刻连同抗蚀剂218一起去除绝缘膜214直到氮化镓生长层12露出为止。由此,去除抗蚀剂218中的设置在比多个小区块13的上表面靠上方的部分、和绝缘膜214中的设置在比多个小区块13的上表面靠上方的部分。
此时,优选使用抗蚀剂218与绝缘膜214的蚀刻速率变得相等的蚀刻条件。通常在氧化硅膜以及氮化硅膜中,可以找出与抗蚀剂成为相同的蚀刻速率的蚀刻条件。由此,能够高精度地使多个小区块13的上表面露出。
在蚀刻工序之后,去除抗蚀剂218中的填埋凹部215的部分。根据以上,形成绝缘膜214。
若以覆盖多个小区块13的方式设置绝缘膜214,则如图7所示,有时在绝缘膜214的表面形成格子状的凹凸。若不涂敷抗蚀剂218,而是与实施方式1同样地仅将绝缘膜214蚀刻到氮化镓生长层12露出为止,则硅基板10之上的绝缘膜214也被蚀刻。因此,有可能绝缘膜214几乎不残留在硅基板10上。
在绝缘膜214使用覆盖性(coverage)为0的膜的极端的例子中,在氮化镓生长层12之上和硅基板10之上,绝缘膜214的厚度变得相同。因此,若对绝缘膜214蚀刻至氮化镓生长层12露出为止,则硅基板10之上的绝缘膜214也被完全去除。
与此相对,在本实施方式中,即使在绝缘膜214的表面形成有凹凸的情况下,也能够在硅基板10之上厚厚地残留绝缘膜214。因此,通过绝缘膜214能够充分地抑制硅基板10的翘曲。
实施方式3
图9是实施方式3所涉及的半导体晶片300的剖视图。半导体晶片300的硅基板310的结构与半导体晶片100不同。在硅基板310的上表面侧形成有多个凸部310a。多个小区块13分别设置于多个凸部310a之上。
接下来,对半导体晶片300的制造方法进行说明。首先,在硅基板310的上表面形成氮化镓生长层12。在该状态下,硅基板310的上表面是平坦的。另外,氮化镓生长层12形成于硅基板310的整个上表面。
接下来,实施蚀刻工序。在蚀刻工序中,首先,在氮化镓生长层12之上形成光致抗蚀剂等掩模层。接下来,使用掩模层通过蚀刻去除氮化镓生长层12的一部分。蚀刻例如为干式蚀刻。由此,氮化镓生长层12被去除成格子状,硅基板310露出。通过蚀刻工序,氮化镓生长层12被分割成多个小区块13。
另外,在硅基板310露出之后也继续进行蚀刻。由此,硅基板310被蚀刻,而在硅基板310形成槽。即,在硅基板310的上表面侧形成多个凸部310a。
接下来,形成绝缘膜14。绝缘膜14填埋相邻的凸部310a之间。之后的工序与实施方式1相同。
在本实施方式中,能够与形成于硅基板310的槽的深度对应地增厚绝缘膜14。因此,能够通过绝缘膜14对硅基板310施加比实施方式1大的应力。另外,即使在氮化镓生长层12的厚度比为了抑制翘曲所需的绝缘膜14的厚度薄的情况下,也能够确保绝缘膜14的厚度。
实施方式4
图10是实施方式4所涉及的半导体晶片400的剖视图。在本实施方式中,在硅基板10的上表面设置有热氧化膜16。在热氧化膜16之上设置有绝缘膜14。热氧化膜16和绝缘膜14形成绝缘层。
接下来,对半导体晶片400的制造方法进行说明。直到使氮化镓生长层12生长的工序为止,与实施方式1相同。在本实施方式中,不去除热氧化膜16。接下来,在热氧化膜16之上形成绝缘膜14。之后的工序与实施方式1相同。
在本实施方式中,由于不去除热氧化膜16,所以能够简化制造工序。另外,在热氧化膜16施加用于矫正硅基板10的翘曲的应力的情况下,能够将热氧化膜16有效地用于翘曲的抑制。
此外,在各实施方式中说明的技术特征也可以适当地组合来使用。
附图标记说明
10...硅基板;11...区域;12...氮化镓生长层;13...小区块;14...绝缘膜;16...热氧化膜;100、200...半导体晶片;214...绝缘膜;215...凹部;218...抗蚀剂;300...半导体晶片;310...硅基板;310a...凸部;400...半导体晶片。
Claims (19)
1.一种半导体晶片的制造方法,其特征在于,
所述半导体晶片的制造方法具备:
第一工序,在硅基板的上表面形成被分割成多个小区块的氮化镓生长层;和
第二工序,用绝缘膜填埋所述多个小区块之间,
所述绝缘膜对所述硅基板施加与所述氮化镓生长层对所述硅基板施加的应力相反方向的应力。
2.根据权利要求1所述的半导体晶片的制造方法,其特征在于,
所述绝缘膜的厚度为1μm以上,且为所述氮化镓生长层的厚度以下。
3.根据权利要求1或2所述的半导体晶片的制造方法,其特征在于,
所述绝缘膜为氮化硅膜。
4.根据权利要求3所述的半导体晶片的制造方法,其特征在于,
所述氮化镓生长层对所述硅基板施加压缩应力,
在所述第二工序中,作为工艺气体使用SiH4和NH3,将SiH4相对于NH3的比率设定为0.5以下,并通过等离子体CVD来形成所述绝缘膜。
5.根据权利要求1~4中任一项所述的半导体晶片的制造方法,其特征在于,
所述第二工序具备如下工序:
用所述绝缘膜覆盖所述硅基板的上表面、和所述多个小区块的各侧面以及上表面,并在所述绝缘膜中的相互相邻的一对小区块之间的部分形成凹部的工序;
以填埋所述凹部的方式,在所述绝缘膜之上设置抗蚀剂的工序;
通过蚀刻去除所述抗蚀剂中的设置在比所述多个小区块的上表面靠上方的部分、和所述绝缘膜中的设置在比所述多个小区块的上表面靠上方的部分,而使所述多个小区块的上表面从所述绝缘膜露出的蚀刻工序;以及
在所述蚀刻工序之后,去除所述抗蚀剂中的填埋所述凹部的部分的工序。
6.根据权利要求1~5中任一项所述的半导体晶片的制造方法,其特征在于,
所述第一工序具备如下工序:
在所述硅基板的上表面形成热氧化膜,用所述热氧化膜将所述硅基板的上表面划分成多个区域的工序;和
在所述多个区域使所述多个小区块分别生长的工序。
7.根据权利要求6所述的半导体晶片的制造方法,其特征在于,
在所述第一工序中,在使所述多个小区块生长之后去除所述热氧化膜。
8.根据权利要求6所述的半导体晶片的制造方法,其特征在于,
在所述第二工序中,在所述热氧化膜之上形成所述绝缘膜。
9.根据权利要求6~8中任一项所述的半导体晶片的制造方法,其特征在于,
所述绝缘膜比所述热氧化膜厚。
10.根据权利要求1~5中任一项所述的半导体晶片的制造方法,其特征在于,
所述第一工序具备如下工序:
在所述硅基板的上表面形成所述氮化镓生长层的工序;和
通过蚀刻去除所述氮化镓生长层的一部分而使所述硅基板露出,由此将所述氮化镓生长层分割成所述多个小区块的蚀刻工序,
在所述蚀刻工序中,在所述硅基板露出之后也继续进行蚀刻,而在所述硅基板形成槽。
11.根据权利要求1~10中任一项所述的半导体晶片的制造方法,其特征在于,
所述绝缘膜从所述硅基板的一端连接到另一端。
12.一种半导体晶片,其特征在于,
所述半导体晶片具备:
硅基板;
氮化镓生长层,设置于所述硅基板的上表面,并被分割成多个小区块;以及
绝缘层,设置于所述硅基板的上表面,并填埋所述多个小区块之间,
所述绝缘层对所述硅基板施加与所述氮化镓生长层对所述硅基板施加的应力相反方向的应力。
13.根据权利要求12所述的半导体晶片,其特征在于,
所述绝缘层的厚度为1μm以上,且为所述氮化镓生长层的厚度以下。
14.根据权利要求12或13所述的半导体晶片,其特征在于,
所述绝缘层包含氮化硅膜。
15.根据权利要求12~14中任一项所述的半导体晶片,其特征在于,
在所述绝缘层,在所述多个小区块中的相互相邻的一对小区块之间形成有凹部。
16.根据权利要求12~15中任一项所述的半导体晶片,其特征在于,
在所述硅基板的上表面侧形成有多个凸部,
所述多个小区块分别设置于所述多个凸部之上。
17.根据权利要求12~15中任一项所述的半导体晶片,其特征在于,
所述绝缘层具有设置于所述硅基板的上表面的热氧化膜、和设置于所述热氧化膜之上的绝缘膜。
18.根据权利要求17所述的半导体晶片,其特征在于,
所述绝缘膜比所述热氧化膜厚。
19.根据权利要求12~18中任一项所述的半导体晶片,其特征在于,
所述绝缘层从所述硅基板的一端连接到另一端。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2019/041534 WO2021079434A1 (ja) | 2019-10-23 | 2019-10-23 | 半導体ウエハおよびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114556529A true CN114556529A (zh) | 2022-05-27 |
Family
ID=73544822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980101276.XA Pending CN114556529A (zh) | 2019-10-23 | 2019-10-23 | 半导体晶片及其制造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20220290327A1 (zh) |
JP (1) | JP6795123B1 (zh) |
KR (1) | KR102518610B1 (zh) |
CN (1) | CN114556529A (zh) |
DE (1) | DE112019007835T5 (zh) |
TW (1) | TWI750847B (zh) |
WO (1) | WO2021079434A1 (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022144009A (ja) * | 2021-03-18 | 2022-10-03 | キオクシア株式会社 | 成膜装置、成膜方法、及び半導体装置の製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10135140A (ja) | 1996-10-28 | 1998-05-22 | Nippon Telegr & Teleph Corp <Ntt> | ヘテロエピタキシャル成長方法、ヘテロエピタキシャル層および半導体発光素子 |
JP3890726B2 (ja) * | 1998-02-24 | 2007-03-07 | 富士電機ホールディングス株式会社 | Iii族窒化物半導体の製造方法 |
KR100767950B1 (ko) * | 2000-11-22 | 2007-10-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 및 그 제조 방법 |
JP4726408B2 (ja) * | 2003-09-19 | 2011-07-20 | シャープ株式会社 | Iii−v族系窒化物半導体素子およびその製造方法 |
JP4160000B2 (ja) * | 2004-02-13 | 2008-10-01 | ドンゴク ユニバーシティ インダストリー アカデミック コーポレイション ファウンデイション | 発光ダイオードおよびその製造方法 |
KR100664986B1 (ko) * | 2004-10-29 | 2007-01-09 | 삼성전기주식회사 | 나노로드를 이용한 질화물계 반도체 소자 및 그 제조 방법 |
JP2005333154A (ja) * | 2005-07-05 | 2005-12-02 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007335484A (ja) * | 2006-06-13 | 2007-12-27 | Mitsubishi Cable Ind Ltd | 窒化物半導体ウェハ |
KR20100085655A (ko) * | 2009-01-21 | 2010-07-29 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성 방법 |
JP2011135058A (ja) * | 2009-11-30 | 2011-07-07 | Honda Motor Co Ltd | 太陽電池素子、カラーセンサ、ならびに発光素子及び受光素子の製造方法 |
JP2011124335A (ja) * | 2009-12-09 | 2011-06-23 | Toyota Motor Corp | 半導体装置 |
US9653286B2 (en) * | 2012-02-14 | 2017-05-16 | Hexagem Ab | Gallium nitride nanowire based electronics |
JP6473017B2 (ja) * | 2015-03-09 | 2019-02-20 | エア・ウォーター株式会社 | 化合物半導体基板 |
GB201507665D0 (en) * | 2015-05-05 | 2015-06-17 | Seren Photonics Ltd | Semiconductor templates and fabrication methods |
JP6544166B2 (ja) * | 2015-09-14 | 2019-07-17 | 信越化学工業株式会社 | SiC複合基板の製造方法 |
JP6724687B2 (ja) * | 2016-08-01 | 2020-07-15 | 日亜化学工業株式会社 | ナノロッドの形成方法及び半導体素子の製造方法 |
-
2019
- 2019-10-23 DE DE112019007835.6T patent/DE112019007835T5/de not_active Withdrawn
- 2019-10-23 WO PCT/JP2019/041534 patent/WO2021079434A1/ja active Application Filing
- 2019-10-23 JP JP2020513664A patent/JP6795123B1/ja active Active
- 2019-10-23 KR KR1020227006023A patent/KR102518610B1/ko active IP Right Grant
- 2019-10-23 US US17/625,084 patent/US20220290327A1/en active Pending
- 2019-10-23 CN CN201980101276.XA patent/CN114556529A/zh active Pending
-
2020
- 2020-10-14 TW TW109135486A patent/TWI750847B/zh active
Also Published As
Publication number | Publication date |
---|---|
TWI750847B (zh) | 2021-12-21 |
JP6795123B1 (ja) | 2020-12-02 |
KR20220041139A (ko) | 2022-03-31 |
KR102518610B1 (ko) | 2023-04-05 |
WO2021079434A1 (ja) | 2021-04-29 |
DE112019007835T5 (de) | 2022-07-07 |
JPWO2021079434A1 (ja) | 2021-11-18 |
TW202123350A (zh) | 2021-06-16 |
US20220290327A1 (en) | 2022-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7291509B2 (en) | Method for fabricating a plurality of semiconductor chips | |
JP5371430B2 (ja) | 半導体基板並びにハイドライド気相成長法により自立半導体基板を製造するための方法及びそれに使用されるマスク層 | |
KR19980079320A (ko) | 고품질 쥐에이엔계층의 선택성장방법, 고품질 쥐에이엔계층 성장기판 및 고품질 쥐에이엔계층 성장기판상에 제작하는 반도체디바이스 | |
JP4522301B2 (ja) | 半導体基板および半導体装置 | |
US8058705B2 (en) | Composite material substrate | |
US20060220042A1 (en) | Semiconductor device and fabrication method of the same | |
JP2006523033A (ja) | シリコン上に単結晶GaNを成長させる方法 | |
JP5192785B2 (ja) | 窒化物半導体装置の製造方法 | |
US10134870B2 (en) | Semiconductor structure and method of manufacturing the same | |
US7279344B2 (en) | Method of forming a nitride-based semiconductor | |
US20090085055A1 (en) | Method for Growing an Epitaxial Layer | |
KR101021775B1 (ko) | 에피택셜 성장 방법 및 이를 이용한 에피택셜층 적층 구조 | |
KR20180088878A (ko) | 결정질 기판 상에 반극성 질화물 층을 획득하기 위한 방법 | |
KR102518610B1 (ko) | 반도체 웨이퍼 및 그 제조 방법 | |
US20070298592A1 (en) | Method for manufacturing single crystalline gallium nitride material substrate | |
JPS62213117A (ja) | 半導体素子の製造方法 | |
US9947530B2 (en) | Method of manufacturing nitride semiconductor substrate | |
EP2869331A1 (en) | Episubstrates for selective area growth of group iii-v material and a method for fabricating a group iii-v material on a silicon substrate | |
KR100833897B1 (ko) | 에피택셜 성장 방법 | |
KR100323710B1 (ko) | 질화갈륨 반도체 레이저 기판의 제조방법 | |
JP2004281869A (ja) | 薄膜形成方法及び薄膜デバイス | |
TWI844049B (zh) | 具有包含氮化鋁銦的阻障層的半導體結構及其生長方法 | |
JPH05267175A (ja) | 化合物半導体基板 | |
JP2010129938A (ja) | 電子デバイスの製造方法 | |
CN110783395A (zh) | 半导体结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |