JP2019504489A - Dram装置用の不均一ゲート酸化物厚さ - Google Patents
Dram装置用の不均一ゲート酸化物厚さ Download PDFInfo
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Abstract
Description
Claims (15)
- ダイナミック・ランダムアクセス・メモリ(DRAM)デバイスを形成する方法において、
基板に形成された窪みを有するフィン付き基板を設けるステップと、及び
前記窪みの側壁表面にイオン注入を実施して、不均一厚さのゲート酸化物層を形成する酸化物層形成ステップであって、前記側壁表面の頂部区域におけるゲート酸化物層の厚さが前記側壁表面の底部区域におけるゲート酸化物層の厚さよりも大きくなるように形成する、該酸化物層形成ステップと、を備える、方法。 - 請求項1記載の方法において、さらに、一連のイオン注入を複数の異なる注入角度で実施するステップを備える、方法。
- 請求項2記載の方法において、さらに、前記一連のイオン注入の実施中に、イオン注入エネルギー及びイオン線量のうち少なくとも一方を変化させるステップを備える、方法。
- 請求項3記載の方法において、さらに、前記注入角度は前記側壁表面に対して測ったものとして、注入角度が減少するにつれて、前記イオン注入エネルギー及びイオン線量を前記一連のイオン注入にわたり増加させるステップを備える、方法。
- 請求項3記載の方法において、さらに、前記側壁表面の前記頂部区域に沿って前記ゲート酸化物の厚さを増加させ、前記ゲート酸化物の厚さが前記フィン付きの基板の頂面近傍で最大となるようにするステップを備える、方法。
- 請求項2記載の方法において、さらに、前記窪みの前記側壁表面に対して前記一連のイオン注入を実施する前に、前記窪み内に基礎酸化物層を形成するステップを備える、方法。
- 請求項2記載の方法において、さらに、前記フィン付きの基板にプラズマを照射するステップを備える、方法。
- 請求項7記載の方法において、さらに、前記フィン付きの基板に対するプラズマ照射、及び前記窪みの前記側壁表面に対する前記一連のイオン注入を同時に実施するステップを備える、方法。
- 請求項7記載の方法において、さらに、前記フィン付きの基板に対するプラズマを照射する前に、前記一連のイオン注入のうち少なくとも1つのイオン注入を実施するステップを備える、方法。
- メモリデバイス用のゲート酸化物層を形成する方法において、
基板に形成された窪みを有するフィン付き基板を設けるステップと、及び
前記窪みの側壁表面に一連のイオン注入を実施して、不均一厚さのゲート酸化物層を形成する酸化物層形成ステップであって、複数の異なる注入角度で一連のイオン注入を前記側壁表面に衝突させて、側壁表面の頂部区域における厚さが側壁表面の底部区域における前記ゲート酸化物層の厚さよりも大きい前記ゲート酸化物層を形成する、該酸化物層形成ステップと、を備える、方法。 - 請求項10記載の方法において、さらに、前記一連のイオン注入の実施中に、イオン注入エネルギー及びイオン線量のうち少なくとも一方を変化させるステップを備える、方法。
- 請求項11記載の方法において、さらに、前記注入角度は前記側壁表面に対して測ったものとして、注入角度が減少するにつれて、前記イオン注入エネルギー及びイオン線量を前記一連のイオン注入にわたり増加させるステップを備える、方法。
- ダイナミック・ランダムアクセス・メモリ(DRAM)デバイスにおいて、
基板に窪みを画定するフィンのセットであって、前記窪みは側壁表面及び底面を有する、該フィンのセットと、及び
前記窪みの前記側壁表面及び前記底面に沿って形成されたゲート酸化物であって、前記側壁表面の頂部区域に沿う前記ゲート酸化物の厚さが前記側壁表面の底部区域に沿う前記ゲート酸化物の厚さよりも大きい、該ゲート酸化物と
を備える、DRAMデバイス。 - 請求項13記載のDRAMデバイスにおいて、前記フィン付きの基板はSiであり、前記ゲート酸化物はSiO2である、DRAMデバイス。
- 請求項13記載のDRAMデバイスにおいて、前記側壁表面の頂部区域に沿う前記ゲート酸化物の厚さは、前記フィン付きの基板の頂面に向かって増大する、DRAMデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/978,305 US10204909B2 (en) | 2015-12-22 | 2015-12-22 | Non-uniform gate oxide thickness for DRAM device |
US14/978,305 | 2015-12-22 | ||
PCT/US2016/063458 WO2017112276A1 (en) | 2015-12-22 | 2016-11-23 | Non-uniform gate oxide thickness for dram device |
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JP2019504489A true JP2019504489A (ja) | 2019-02-14 |
JP2019504489A5 JP2019504489A5 (ja) | 2019-12-26 |
JP7176951B2 JP7176951B2 (ja) | 2022-11-22 |
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CN112185963B (zh) * | 2020-09-30 | 2022-06-03 | 福建省晋华集成电路有限公司 | 存储器及其形成方法 |
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US20170179133A1 (en) | 2017-06-22 |
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CN108475679A (zh) | 2018-08-31 |
WO2017112276A1 (en) | 2017-06-29 |
KR102635849B1 (ko) | 2024-02-13 |
TW201725664A (zh) | 2017-07-16 |
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