TWI493630B - 用於在相同晶片上形成具有各種摻雜之鰭式場效電晶體之方法及結構 - Google Patents
用於在相同晶片上形成具有各種摻雜之鰭式場效電晶體之方法及結構 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 59
- 239000004065 semiconductor Substances 0.000 claims description 70
- 239000002019 doping agent Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 42
- 238000005468 ion implantation Methods 0.000 claims description 38
- 229910052732 germanium Inorganic materials 0.000 claims description 29
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 22
- 239000007943 implant Substances 0.000 claims description 19
- 238000001459 lithography Methods 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 238000007743 anodising Methods 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 125000005842 heteroatom Chemical group 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000002513 implantation Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 4
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 229910052717 sulfur Inorganic materials 0.000 description 4
- 239000011593 sulfur Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description
本發明係關於半導體製造,且更特定而言係關於用於在無關鍵遮罩步驟或結構之情況下形成finFET之多個摻雜區域的結構及方法。
鰭式場效電晶體(finFET)已作為用於互補金屬氧化物半導體(CMOS)技術之連續按比例調整的未來器件選擇中之一者加以廣泛研究。大多數CMOS應用需要相同晶片上之各種類型之器件。舉例而言,微處理器晶片通常包括具有各種臨限電壓(Vt)(例如,高Vt、正常Vt及低Vt)之n型及p型(nFET及pFET)器件兩者。具有不同Vt之finFET在鰭部分中需要不同摻雜。
用於形成具有不同鰭摻雜之finFET的先前技術做法複雜且昂貴,因為該等先前技術做法需要用於形成鰭及遮罩一些鰭同時摻雜其他鰭之多個關鍵微影步驟。大體上,此等方法需要遮罩半導體晶圓之一部分,執行一摻雜技術或其他製程,移除遮罩,在晶圓之另一部分上形成一新遮罩,後續接著執行一不同摻雜技術或其他製程及移除該新遮罩。
必須準確地執行該等遮罩及摻雜製程以確保該等器件之適當操作。此情形招致相當大之時間及成本。
一種用於一積體電路之特徵之製造的方法包括在一半導體器件之一表面上圖案化一第一半導體結構,及在該第一半導體結構之相對側上磊晶生長半導體材料以形成鰭。將一第一傾斜離子植入應用於該第一半導體結構之一側以摻雜該一側上之一各別鰭。選擇性地移除該第一半導體結構以暴露該等鰭。使用該等鰭形成鰭式場效電晶體。
一種用於一積體電路之特徵之製造的方法包括:在一半導體基板之一表面上圖案化心軸(mandrels);在該等心軸之一周邊周圍形成間隔物;應用一第一傾斜離子植入以引入一第一摻雜,以使得該等間隔物及該等心軸形成一阻隔遮罩以將該第一摻雜導引至該阻隔遮罩之一側上的一底層半導體層中;在與該第一傾斜離子植入相反之一方向上應用一第二傾斜離子植入以引入一第二摻雜,以使得該阻隔遮罩將該第二摻雜導引至該阻隔遮罩之一相對側上的該底層半導體層中;相對於該等間隔物選擇性地移除該等心軸;使用該等間隔物作為一蝕刻遮罩來圖案化該底層半導體層以形成具有該第一摻雜之鰭及具有第二摻雜之鰭;使具有該第一摻雜之該等鰭及具有第二摻雜之鰭退火;及使用該等鰭形成鰭式場效電晶體。
此等及其他特徵及優點將自本發明之說明性實施例的以下詳細描述變得顯而易見,此詳細描述將結合所附圖式加以閱讀。
本發明將參看以下諸圖提供較佳實施例之以下描述中的細節。
根據本發明之原理,揭示一種用於在相同晶片上形成具有不同鰭摻雜之finFET的方法及結構。在一說明性實施例中,藉由磊晶生長在犧牲性心軸(例如,多孔矽或SiGe)之側壁上形成鰭。藉由第一傾斜離子植入來摻雜犧牲性心軸之第一側上的鰭,且藉由第二離子植入來不同地摻雜犧牲性心軸之第二側上的鰭。在另一實施例中,藉由第一傾斜離子植入來摻雜犧牲性心軸之第一側上的鰭,且犧牲性心軸之第二側上的鰭保持不摻雜。不同地摻雜第一鰭及第二鰭以基於極性、臨限電壓或其兩者形成兩個或兩個以上不同器件。
應理解,將根據給定之說明性架構來描述本發明;然而,可在本發明之範疇內變化其他架構、結構、基板材料及製程特徵及步驟。
該等結構及製程步驟較佳為用於積體電路晶片之設計的一部分。晶片設計可以圖形電腦程式設計語言形成,且儲存於電腦儲存媒體(諸如,磁碟、磁帶、實體硬碟機或諸如在儲存存取網路中之虛擬硬碟機)中。若設計者不製造晶片或不製造用以製造晶片之光微影遮罩,則設計者可藉由實體構件(例如,藉由提供儲存設計之儲存媒體的複本)或以電子方式(例如,經由網際網路)將所得設計直接或間接地傳輸至該等實體。接著將儲存之設計轉換為適當格式(例如,GDSII)以用於製造光微影遮罩,該等光微影遮罩通常包括待形成於晶圓上的所提到之晶片設計的多個複本。該等光微影遮罩用以界定待蝕刻或另外處理的晶圓之區域(及/或其上之層)。
如本文中所描述之方法可用於製造積體電路晶片。所得積體電路晶片可由製造商以原始晶圓形式(亦即,作為具有多個未封裝晶片之單一晶圓)、作為裸晶粒、或以封裝形式散佈。在以封裝形式散佈之狀況下,晶片安裝於單晶片封裝(諸如,塑膠載體,其具有附著至主機板或其他較高階載體的引線)中或多晶片封裝(諸如,具有任一或兩個表面互連或內埋式互連的陶瓷載體)中。在任一狀況下,接著將該晶片與其他晶片、離散電路元件,及/或其他信號處理器件整合,作為(a)中間產品(諸如,主機板)或(b)最終產品之一部分。該最終產品可為包括積體電路晶片之任何產品,範圍遍及自玩具及其他低端應用至具有顯示器、鍵盤或其他輸入器件及中央處理器之進階電腦產品。
現參看諸圖,其中相同數字表示相同或類似元件,且最初參看圖1,絕緣體上覆半導體基板(SOI)10展示為具有形成於其上之蓋或襯墊層或介電襯裡18。SOI基板10可包括具有絕緣層(例如,內埋式氧化物(BOX)層)14之矽基層12及氧化物上覆矽層16。應理解,基板10可包括任何合適材料且不限於SOI。舉例而言,基板10可為SOI或塊體基板,該SOI或塊體基板可包括砷化鎵、單晶矽、鍺,或可應用本發明之原理的任何其他材料或材料之組合。在一些實施例中,基板10進一步包含在先前製程步驟中形成於半導體基板上或半導體基板中之其他特徵或結構。
介電襯裡18可包括使得能夠選擇性地蝕刻底層材料(例如,層16)之一介電材料。在一實施例中,層16為單晶矽且襯裡18可包括氮化矽(氮化物)或氧化矽(氧化物)。襯裡18沈積或熱生長於層16上。
參看圖2,藉由(例如)微影圖案化製程來圖案化襯裡18。一旦圖案化襯裡18,便可使用諸如反應性離子蝕刻之蝕刻製程來移除層16之一部分。襯裡18可充當蝕刻遮罩以顯現層16。襯裡18之圖案化可包括同時圖案化諸如層16之底層。或者,可圖案化襯裡18且接著將其用作遮罩以蝕刻層16之材料。在此實例中,層16包括矽。層16形成心軸20。
參看圖3,將心軸20轉化為晶種材料22以促進心軸20之側壁上的磊晶生長,例如,藉由一已知製程(例如,摻雜,後續接著陽極處理)將心軸20轉化為多孔矽。應理解,亦可使用其他方法來形成心軸20。舉例而言,可在任一表面上形成多晶矽心軸。在一實施例中,心軸20包含矽鍺,且可省略圖3中之轉化步驟。
參看圖4,在心軸22之側壁上生長鰭24及26。在一實施例中,在多孔矽22之側壁上磊晶生長矽鰭24及26。磊晶矽鰭24及26可未經摻雜,或在磊晶生長期間原位摻雜,或在磊晶生長之後摻雜。為了簡單起見,用於鰭24及26之磊晶矽未經摻雜。在一實施例中,材料22包含矽鍺且矽鰭24及26磊晶生長於矽鍺22之側壁上。
參看圖5,執行第一傾斜離子植入28以摻雜材料22(例如,多孔矽)之一側上的鰭24。傾斜離子植入28包括藉由諸如用於nFET之磷(P)、砷(As)等或用於pFET之硼(B)、銦(In)、銻(Sb)等的摻雜劑來轟擊鰭24。可變化密度、時間及能量以給所得器件提供不同臨限電壓。植入之角度可在相對於垂直於器件之主表面之垂線約5度至約75度之間。其他離子類型包括但不限於鍺(Ge)、氮(N)、氟(F)、碳(C)、硫(S)、矽(Si)等且亦可使用其他角度之攻擊。取決於鰭厚度及植入物質,植入劑量可以自1×1012
/cm2
至5×1015
/cm2
為範圍,植入能量可以自0.5 KeV至100 KeV為範圍。應注意,使用傾斜植入以能夠選擇轟擊鰭24(或鰭26)之哪些部分。其他表面可暴露於轟擊或經保護而免受轟擊以確保摻雜劑密度及類型適用於提供所得器件之恰當操作。
應理解,鰭24及26可形成為任何寬度。在一尤其適用之實施例中,鰭24及26包括次最小特徵大小之寬度。可控制磊晶生長以提供任何大小之寬度,但特定言之,提供小於可藉由微影處理達成之最小特徵大小的大小。
參看圖6,執行第二傾斜離子植入30以摻雜材料22(例如,多孔矽)之另一側上的鰭26。若在鰭26中不需要額外摻雜劑,則可跳過第二傾斜離子植入。如所提及,可在鰭24及/或26之形成期間包括摻雜劑。
傾斜離子植入30包括藉由諸如用於n型摻雜劑之P、As等或用於p型摻雜劑之B等的摻雜劑來轟擊鰭26。可變化密度、時間及能量以給所得器件提供不同臨限電壓。植入之角度可在相對於垂直於器件之主表面之垂線約5度至約75度之間。其他離子類型包括但不限於鍺(Ge)、氮(N)、氟(F)、碳(C)、硫(S)、矽(Si)等且亦可使用其他角度之攻擊。取決於鰭厚度及植入物質,植入劑量可以自1×1012
/cm2
至5×1015
/cm2
為範圍,植入能量可以自0.5 KeV至100 KeV為範圍。應注意,使用傾斜植入以能夠選擇轟擊鰭26(或鰭24)之哪些部分。其他表面可暴露於轟擊或經保護而免受轟擊以確保恰當地使用摻雜劑密度及類型來提供所得器件之恰當操作。
應理解,在不形成阻隔遮罩或層之情況下有利地執行第一及/或第二離子植入製程。以此方式,即使進行兩個或兩個以上不同摻雜步驟,仍自製程記錄消除許多製程步驟。
參看圖7,移除襯墊層18及材料22(例如,多孔矽或矽鍺)。此等操作可包括一或多個蝕刻步驟,對於底層(例如,BOX層14)及鰭24及26而言,該一或多個蝕刻步驟為選擇性的。所得鰭24及26可經進一步處理以形成FET。在此實例中,鰭24及鰭26係不同地摻雜且可包括具有如表1中所闡述之以下說明性組合。
參看圖8,藉由兩個鰭24及26中之不同摻雜,達成不同電學性質。因為鰭24及26一起形成於同一層14上且已加以摻雜,所以促進finFET之進一步處理。單一閘極介電質32沈積後續接著單一閘極導體34沈積係在不同類型之鰭上執行且連同其他閘極層及側面間隔物一起同時圖案化以形成電晶體或其他組件。有利的是,後續處理可如同鰭相同一樣來處理該等鰭。換言之,因為在無遮罩傾斜離子植入期間預先考慮且考量鰭24及26之材料及摻雜差別,所以此等結構可同時經進一步處理。FinFET 40及42可用作CMOS器件或可包括具有不同臨限電壓等之單極性之器件(NFET或PFET)。
根據本發明之原理,可使用其他方法來提供類似結果。舉例而言,圖9至圖13提供一種該替代做法。
參看圖9,絕緣體上覆半導體基板(SOI)10展示為具有形成於其上之襯墊層18(例如,氧化物或氮化物)及心軸46。SOI基板10可包括具有內埋式氧化物層(BOX層)14之矽基層12及氧化物上覆矽層16。應理解,基板10可包括任何合適材料且不限於SOI。舉例而言,基板10可包括砷化鎵、單晶矽、鍺、塊體材料或任何其他材料或材料之組合。在一些實施例中,基板10進一步包含在先前製程步驟中形成於半導體基板上或半導體基板中之其他特徵或結構。
心軸46形成於層18上且較佳使用一微影製程來圖案化,該微影製程可包括一抗蝕劑層(未圖示)及微影圖案化。層18可藉由一沈積製程形成且較佳包括氧化物(諸如,二氧化矽)或氧化物之一形式。心軸46可自非晶矽或多晶矽(多晶矽)材料形成。在心軸46之側壁周圍添加間隔物48。間隔物48可包括氮化矽材料。可保形地沈積間隔物材料,後續接著用以自層18之表面及心軸46之頂部移除間隔物材料的一蝕刻。亦可使用其他材料及製程步驟以達成圖9中所描繪之結構。
參看圖10,第一傾斜離子植入50包括藉由諸如用於n型摻雜劑之P、As等或用於p型摻雜劑之B等的摻雜劑來轟擊心軸46及間隔物48。該等摻雜劑具有足以進入並保持於層16內之能量,層16包括諸如矽之半導體材料。可變化摻雜劑之密度、時間及能量以給所得器件提供不同臨限電壓。植入之角度可在相對於垂直於器件之主表面之垂線約5度至約75度之間。其他離子類型包括但不限於鍺(Ge)、氮(N)、氟(F)、碳(C)、硫(S)、矽(Si)等且亦可使用其他角度之攻擊。取決於鰭厚度及植入物質,植入劑量可以自1×1012
/cm2
至5×1015
/cm2
為範圍,植入能量可以自0.5 KeV至100 KeV為範圍。應注意,使用傾斜植入以能夠選擇在間隔物/心軸結構(48,46)之間轟擊層16之哪些部分。其他表面可暴露於轟擊或經保護而免受轟擊以確保恰當地使用摻雜劑密度及類型來提供所得器件之恰當操作。在此說明中,使用n型摻雜劑來形成摻雜區域60。應理解,可能已替代地使用p型摻雜劑。
參看圖11,第二傾斜離子植入52包括以與區域60相反之極性之摻雜劑或以一不同摻雜劑密度來轟擊心軸46及間隔物48以形成不同臨限電壓器件。該等離子可包括(例如)用於n型摻雜劑之P、As等或用於p型摻雜劑之B等。在此說明中,若第一植入包括n型摻雜劑,則第二植入包括p型摻雜劑(或反之亦然)。該等摻雜劑具有足以進入並保持於層16內之能量,層16包括諸如矽之半導體材料。可變化摻雜劑之密度、時間及能量以(例如)為所得器件提供不同臨限電壓。植入之角度可在相對於垂直於器件之主表面之垂線約5度至約75度之間。其他離子類型包括但不限於鍺(Ge)、氮(N)、氟(F)、碳(C)、硫(S)、矽(Si)等且亦可使用其他角度之攻擊。取決於層18之厚度、層16中之所要深度及植入物質,植入劑量可以自1×1012
/cm2
至5×1015
/cm2
為範圍,且植入能量可以自0.5 KeV至100 KeV為範圍。應注意,使用傾斜植入以能夠選擇使用層16之哪些部分來在間隔物48與心軸結構46之間形成區域62。
參看圖12,藉由一蝕刻製程來移除心軸46,後續接著圖案化及蝕刻襯墊層18及(在此實例中)矽層16。可使用間隔物48作為阻隔遮罩來執行該圖案化及蝕刻以向下蝕刻至層14。間隔物48較佳包括次最小特徵大小(例如,小於可藉由微影得到之寬度的寬度)。在蝕刻層18及16之後,形成鰭64及66。鰭64及66分別包括摻雜區域60及62之剩餘部分。歸因於傾斜植入,鰭64及66之摻雜區域可能不具有均一濃度之摻雜劑。在圖13中,可應用一退火製程擴散鰭64及66內之摻雜劑以提供摻雜劑之較均勻之散佈且增大鰭64及66中之作用區域的大小。處理可如以前所述繼續以完成finFET之製造且保持晶片或晶圓之部分。
參看圖14,一種用於積體電路之特徵之製造的方法包括在區塊102中在半導體基板之一表面上圖案化第一半導體結構。該第一半導體結構較佳包括半導體材料(矽)。在區塊103中,處理第一結構以允許在第一半導體結構之側壁上磊晶生長。該處理包括在區塊105中藉由摻雜及陽極處理而形成多孔矽。第一結構可包括適合於磊晶生長之材料(例如,SiGe),因而可避免處理。
在區塊106中,在第一半導體結構之相對側上磊晶生長半導體材料以形成鰭。此操作可包括在第一半導體結構之多孔矽(或SiGe)上磊晶生長矽。可在半導體材料之磊晶生長期間引入摻雜劑。在區塊107中,可控制半導體材料之磊晶生長以提供小於可藉由微影方法達成之最小特徵大小的寬度。
在區塊108中,將第一傾斜離子植入應用於第一半導體結構之一側以摻雜該一側上之一各別鰭。另一側保持於遮蔽中且因此不被摻雜。在區塊110中,視情況將第二傾斜離子植入應用於第一半導體結構之相對側以摻雜該相對側上之一各別鰭。該第一傾斜離子植入可包括藉由第一極性摻雜劑摻雜該一側,且該第二傾斜離子植入包括藉由第二極性摻雜劑摻雜該相對側。另外,該第一傾斜離子植入可包括以第一摻雜劑密度摻雜該一側,且該第二傾斜離子植入可包括以第二摻雜劑密度摻雜相對側。亦可將密度及摻雜劑類型之組合用於每一植入製程。
在區塊112中,選擇性地移除第一半導體結構以暴露鰭。在區塊114中,使用該等鰭形成鰭式場效電晶體。
參看圖15,說明性地展示用於積體電路之特徵之製造的另一方法。在區塊202中,在半導體基板之一表面上圖案化心軸。在區塊204中,在該等心軸之周邊周圍形成間隔物。該等間隔物較佳包括小於可藉由微影方法達成之最小特徵大小的特徵大小。
在區塊206中,應用第一傾斜離子植入以引入第一摻雜,以使得間隔物及心軸形成一阻隔遮罩以將第一摻雜導引至阻隔遮罩之一側上的底層半導體層中。在區塊208中,在與該第一傾斜離子植入相反之方向上應用第二傾斜離子植入以引入第二摻雜,以使得阻隔遮罩將第二摻雜導引至該阻隔遮罩之相對側上的底層半導體層中。該第一摻雜可包括第一極性摻雜劑,且該第二摻雜可包括第二極性摻雜劑及/或第一摻雜可包括第一摻雜劑密度,且第二摻雜可包括第二摻雜劑密度。
在區塊210中,相對於該等間隔物選擇性地移除該等心軸。在區塊212中,使用該等間隔物作為蝕刻遮罩來圖案化該底層半導體層以形成具有該第一摻雜之鰭及具有該第二摻雜之鰭。在區塊214中,使具有該第一摻雜之鰭及具有該第二摻雜之鰭退火以擴散及散佈鰭中之摻雜劑。在區塊216中,使用該等鰭形成鰭式場效電晶體。該等鰭較佳包括小於可藉由微影方法達成之最小特徵大小的特徵大小。
已描述用於在相同晶片上形成具有多個摻雜區域之finFET之方法及結構的較佳實施例(其意欲為說明性的而非限制性的),應注意,熟習此項技術者可根據以上教示進行修改及變化。因此應理解,可對所揭示之特定實施例進行若干改變,該等改變在由附加申請專利範圍所概述之本發明之範疇內。在以專利法所需的細節及特殊性而如此描述本發明之態樣之後,在附加申請專利範圍中闡述受專利證書保護之所主張且所要之內容。
10...絕緣體上覆半導體基板(SOI)
12...矽基層
14...絕緣層
16...氧化物上覆矽層
18...介電襯裡
20...心軸
22...晶種材料
24...磊晶矽鰭
26...磊晶矽鰭
28...第一傾斜離子植入
30...第二傾斜離子植入
32...單一閘極介電質
34...單一閘極導體
40...鰭式場效電晶體(FinFET)
42...鰭式場效電晶體(FinFET)
46...心軸
48...間隔物
50...第一傾斜離子植入
52...第二傾斜離子植入
60...摻雜區域
62...摻雜區域
64...鰭
66...鰭
圖1為絕緣體上覆半導體基板的透視圖,該基板具有形成於其上之襯墊層;
圖2為圖1中之器件的透視圖,其展示襯墊層及半導體層經圖案化;
圖3為圖2中之器件的透視圖,其展示半導體層藉由一處理程序而轉化;
圖4為圖3中之器件的透視圖,其展示半導體層之側壁上磊晶生長半導體鰭;
圖5為圖4中之器件的透視圖,該器件經受半導體層之側壁上之鰭中的一者的第一傾斜離子植入;
圖6為圖5中之器件的透視圖,該器件經受半導體層之側壁上之鰭中的另一者的第二傾斜離子植入;
圖7為在已移除襯墊層及半導體層之後的圖6中之器件的透視圖;
圖8為圖7中之器件的透視圖,其展示用以維持底層鰭之可見性且用以展示finFET之形成的閘極介電質及閘極導體的一小部分;
圖9為絕緣體上覆半導體基板的橫截面圖,該基板具有形成於其上之襯墊層、心軸及間隔物;
圖10為圖9中之器件的橫截面圖,該器件經受第一傾斜離子植入;
圖11為圖10中之器件的橫截面圖,該器件經受第二傾斜離子植入;
圖12為在已移除心軸且已使用間隔物作為遮罩蝕刻半導體層之後的圖11中之器件的橫截面圖;
圖13為在用於形成finFET的鰭之退火之後的圖12中之器件的橫截面圖;
圖14為展示用於形成具有相同晶片上之不同場效電晶體之半導體器件之一說明性方法的方塊圖;及
圖15為展示用於形成具有相同晶片上之不同場效電晶體之半導體器件之另一說明性方法的方塊圖。
(無元件符號說明)
Claims (16)
- 一種用於一積體電路之特徵之製造的方法,其包含:在一半導體基板之一表面上圖案化一第一半導體結構;在該第一半導體結構之相對側上磊晶生長半導體材料以形成一第一鰭及一第二鰭;將一第一傾斜離子植入應用於該第一半導體結構之一側以摻雜該一側上之該第一鰭而未摻雜該第二鰭;選擇性地移除該第一半導體結構以暴露該第一鰭及該第二鰭;及使用該第一鰭及該第二鰭形成鰭式場效電晶體。
- 如請求項1之方法,其進一步包含處理該第一結構以允許在該第一結構之側壁上磊晶生長。
- 如請求項2之方法,其中該第一半導體結構包括矽,且處理該第一半導體結構包括藉由摻雜及陽極處理(anodizing)而形成多孔矽。
- 如請求項3之方法,其中磊晶生長半導體材料包括在該第一半導體結構之該多孔矽上磊晶生長矽。
- 如請求項1之方法,其進一步包含將一第二傾斜離子植入應用於該第一半導體結構之一相對側以摻雜該第二鰭而未摻雜該第一鰭。
- 如請求項5之方法,其中應用該第一傾斜離子植入包括藉由一第一極性摻雜劑摻雜該一側,且應用該第二傾斜離子植入包括藉由一第二極性摻雜劑摻雜該相對側。
- 如請求項5之方法,其中應用該第一傾斜離子植入包括以一第一摻雜劑密度摻雜該一側,且應用該第二傾斜離子植入包括以一第二摻雜劑密度摻雜該相對側。
- 如請求項1之方法,其中磊晶生長半導體材料包括在該半導體材料之磊晶生長期間引入摻雜劑。
- 如請求項1之方法,其中磊晶生長半導體材料包括磊晶生長該半導體材料以使得該半導體材料之一寬度包括小於可藉由一微影方法達成之一最小特徵大小的一大小。
- 如請求項1之方法,其中該第一半導體結構包括允許直接磊晶生長之一材料。
- 如請求項1之方法,其中該第一半導體結構包括矽鍺。
- 一種用於一積體電路之特徵之製造的方法,其包含:在一半導體基板之一表面上圖案化心軸;在該等心軸之一周邊周圍形成間隔物;應用一第一傾斜離子植入以引入一第一摻雜,以使得該等間隔物及該等心軸形成一阻隔遮罩以將該第一摻雜導引至該阻隔遮罩之一側上的一底層半導體層中;在與該第一傾斜離子植入相反之一方向上應用一第二傾斜離子植入以引入一第二摻雜,以使得該阻隔遮罩將該第二摻雜導引至該阻隔遮罩之一相對側上的該底層半導體層中;相對於該等間隔物選擇性地移除該等心軸;使用該等間隔物作為一蝕刻遮罩來圖案化該底層半導體層以形成具有該第一摻雜之鰭及具有第二摻雜之鰭; 使具有該第一摻雜之該等鰭及具有第二摻雜之鰭退火;及使用該等鰭形成鰭式場效電晶體。
- 如請求項12之方法,其中該第一摻雜包括一第一極性摻雜劑,且該第二摻雜包括一第二極性摻雜劑。
- 如請求項12之方法,其中該第一摻雜包括一第一摻雜劑密度,且該第二摻雜包括一第二摻雜劑密度。
- 如請求項12之方法,其中形成間隔物包括形成具有小於可藉由一微影方法達成之一最小特徵大小之一特徵大小的間隔物。
- 如請求項12之方法,其中該等鰭具有小於可藉由一微影方法達成之一最小特徵大小的一特徵大小。
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US20070099350A1 (en) * | 2005-10-27 | 2007-05-03 | International Business Machines Corporation | Structure and method of fabricating finfet with buried channel |
US20080206934A1 (en) * | 2007-02-23 | 2008-08-28 | Jones Robert E | Forming semiconductor fins using a sacrificial fin |
Also Published As
Publication number | Publication date |
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GB201202927D0 (en) | 2012-04-04 |
US20110129978A1 (en) | 2011-06-02 |
GB2488642B (en) | 2013-12-11 |
TW201135850A (en) | 2011-10-16 |
CN102640273B (zh) | 2015-02-11 |
GB2488642A (en) | 2012-09-05 |
WO2011067049A1 (en) | 2011-06-09 |
US8021949B2 (en) | 2011-09-20 |
DE112010004804B4 (de) | 2016-06-30 |
CN102640273A (zh) | 2012-08-15 |
DE112010004804T5 (de) | 2012-11-15 |
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