JP2019057557A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
Description
第1導電型の第1半導体層(11)を有する半導体基板(10)の主面(10a)側に、素子形成領域(A)及び外周耐圧領域(B)を有する半導体装置(1)において、
上記素子形成領域は、上記主面側の表層部に、パワー素子を構成する第2導電型の第2半導体領域(21)を有するセル領域(A1)及び回路素子を構成する第2導電型の第3半導体領域(121)を有する回路素子領域(A2)を有しており、
上記回路素子領域は、上記外周耐圧領域と上記セル領域の間に配置されると共に、
上記外周耐圧領域は、上記素子形成領域との境界領域(B1)となる上記表層部に、第2導電型の第4半導体領域(122、123)を備えており、
上記第4半導体領域内には、1以上の耐圧領域(4A、4B)が設けられ、少なくとも1つの上記耐圧領域は、上記セル領域及び上記回路素子領域よりも耐圧が低く設定されている、半導体装置にある。
第1導電型の第1半導体層(11)を有する半導体基板(10)の主面(10a)側に、素子形成領域(A)及び外周耐圧領域(B)を有する半導体装置(1)において、
上記素子形成領域は、上記主面側の表層部に、パワー素子を構成する第2導電型の第2半導体領域(21)を有するセル領域(A1)及び回路素子を構成する第2導電型の第3半導体領域(121)を有する回路素子領域(A2)を有すると共に、上記回路素子領域を取り囲んで上記セル領域が配置されており、
上記外周耐圧領域は、上記素子形成領域との境界領域(B1)となる上記表層部に、第2導電型の第4半導体領域(123)を備えており、
上記第4半導体領域内には、1以上の耐圧領域(4A)が設けられ、少なくとも1つの上記耐圧領域は、上記セル領域及び上記回路素子領域よりも耐圧が低く設定されている、半導体装置にある。
なお、特許請求の範囲及び課題を解決する手段に記載した括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものであり、本発明の技術的範囲を限定するものではない。
以下に、半導体装置に係る実施形態1について、図面を参照して説明する。図1、図2に示すように、本形態の半導体装置1は、パワー素子を構成するセル領域A1と回路素子を構成する回路素子領域A2とを同一チップに設けたインテリジェントパワー素子として構成されている。図3に示すように、このような半導体装置1は、例えば、内燃機関の点火装置に適用されて、点火コイル101の通電を制御するイグナイタ部100を構成することができる。イグナイタ部100は、点火コイル101への通電を制御する点火用パワー素子102(すなわち、セル領域A1に相当)と、これを制御又は保護する回路(すなわち、回路素子領域A2に相当)を備えている。
回路素子3及びIGBTセル2の構成については、詳細を後述する。
なお、図1ではp型ウェル領域12の深さは、回路素子領域A2及び外周耐圧領域Bにおいて一定であり、端部を除いて深さ方向のpn接合部は、概略平面状となる構成としている。
また、以下の実施形態等において用いる符号のうち、既出の実施形態において用いた符号と同一のものは、特に示さない限り、既出の実施形態におけるものと同様の構成要素等を表す。
図8に示す参考例2において、素子形成領域Aには、セル領域A1に隣接する回路素子領域A2に、p型ウェル領域12の内周端部と重なるように、p+型半導体層17が配置されている。p+型半導体層17は、p型ウェル領域12よりも深く形成されて、n-型のドリフト層11に到達する一方、上方に配置されるセル領域A1のエミッタ電極13と、層間絶縁膜37に設けられるコンタクトホールを介して、直接接触している。このとき、ドリフト層11とp+型半導体層17とのpn接合部は、p型ウェル領域12とのpn接合部よりも不純物勾配が大きく、耐圧が低くなっている。
図9に実施形態2として示すように、素子形成領域Aにおいて、回路素子部3の配置やサイズは必ずしも限定されず、適宜変更することができる。また、素子形成領域Aとの境界領域B1に形成される耐圧領域の構成や配置も、適宜変更することができる。
ここでは、図示するように、矩形ループ状の外周耐圧領域Bの内側において、そのコーナー部の1つに近い領域に、概略正方形の回路素子領域A2が配置される。回路素子領域A2は、外周耐圧領域Bの直線部に隣接し、直線部の全長の半部超に亘って設けられる。この直線部の長手方向において、回路素子領域A2が隣接配置されない領域と、素子形成領域Aの残りの領域には、セル領域A1が設けられる。セル領域A1及び回路素子領域A2の基本構成は、上記実施形態1と同様とすることができる。
なお、必ずしも耐圧領域4A、4Bを素子形成領域Aの全体を取り囲んで設けられていなくてもよく、例えば、局所的に電流が集中しやすい領域の近傍に設け、電流集中のおそれがない一部に耐圧領域4を設けない構成とすることもできる。
図11、図12に実施形態3として示すように、素子形成領域Aにおいて、回路素子部3を、外周耐圧領域Bの直線部から離して配置することもできる。ここでは、図11に示すように、矩形ループ状の外周耐圧領域Bの内側において、矩形の下辺側の直線部に近接して、概略矩形の回路素子領域A2が配置される。回路素子領域A2は、外周耐圧領域Bの直線部と所定の間隔をおいて配置され、素子形成領域Aの残りの領域には、セル領域A1が設けられる。すなわち、回路素子領域A2は、セル領域A1にて全体が取り囲まれている。セル領域A1及び回路素子領域A2の基本構成は、上記実施形態1と同様とすることができる。
A1 セル領域
A2 回路素子領域
B 外周耐圧領域
1 半導体装置
10 半導体基板
10a 主面
11 ドリフト層(第1半導体層)
12 p型ウェル領域
121 p型ウェル領域(第3半導体領域)
122、123 p型ウェル領域(第4半導体領域)
21 p型ベース領域(第2半導体領域)
4A、4B 耐圧領域
Claims (9)
- 第1導電型の第1半導体層(11)を有する半導体基板(10)の主面(10a)側に、素子形成領域(A)及び外周耐圧領域(B)を有する半導体装置(1)において、
上記素子形成領域は、上記主面側の表層部に、パワー素子を構成する第2導電型の第2半導体領域(21)を有するセル領域(A1)及び回路素子を構成する第2導電型の第3半導体領域(121)を有する回路素子領域(A2)を有しており、
上記回路素子領域は、上記外周耐圧領域と上記セル領域の間に配置されると共に、
上記外周耐圧領域は、上記素子形成領域との境界領域(B1)となる上記表層部に、第2導電型の第4半導体領域(122、123)を備えており、
上記第4半導体領域内には、1以上の耐圧領域(4A、4B)が設けられ、少なくとも1つの上記耐圧領域は、上記セル領域及び上記回路素子領域よりも耐圧が低く設定されている、半導体装置。 - 上記耐圧領域は、上記素子形成領域の外周を取り囲んで配置される、請求項1に記載の半導体装置。
- 上記第4半導体領域は、上記第3半導体領域と連続して一体的に構成されている、請求項1又は2に記載の半導体装置。
- 第1導電型の第1半導体層(11)を有する半導体基板(10)の主面(10a)側に、素子形成領域(A)及び外周耐圧領域(B)を有する半導体装置(1)において、
上記素子形成領域は、上記主面側の表層部に、パワー素子を構成する第2導電型の第2半導体領域(21)を有するセル領域(A1)及び回路素子を構成する第2導電型の第3半導体領域(121)を有する回路素子領域(A2)を有すると共に、上記回路素子領域を取り囲んで上記セル領域が配置されており、
上記外周耐圧領域は、上記素子形成領域との境界領域(B1)となる上記表層部に、第2導電型の第4半導体領域(123)を備えており、
上記第4半導体領域内には、1以上の耐圧領域(4A)が設けられ、少なくとも1つの上記耐圧領域は、上記セル領域及び上記回路素子領域よりも耐圧が低く設定されている、半導体装置。 - 上記耐圧領域は、上記第2半導体領域の表層部に形成された高濃度の第2導電型領域(42)と、上記第2導電型領域と接続された電極部(41)を備える、請求項1〜4のいずれか1項に記載の半導体装置。
- 上記セル領域は、上記主面(10a)側に設けられる低電位側電極(13)と、上記主面(10a)と反対側に設けられる高電位側電極(14)とに接続されるセル(2、2A)を有しており、
上記耐圧領域の上記電極部は、上記低電位側電極に接続される、請求項5に記載の半導体装置。 - 上記セルは、上記パワー素子の基本単位となる第1セル(2)と、寄生トランジスタ構造を有しない第2セル(2A)とを有し、上記境界領域と隣接する領域には、上記第2セルが配置される、請求項6に記載の半導体装置。
- 上記回路素子領域は、上記セル領域の制御用又は保護用の回路を構成する複数の回路素子(3)を有している、請求項1〜7のいずれか1項に記載の半導体装置。
- 上記第4半導体領域内には、複数の上記耐圧領域が設けられ、複数の上記耐圧領域の全部が、上記セル領域及び上記回路素子領域よりも耐圧が低く設定されている、
請求項1〜8のいずれか1項に記載の半導体装置。
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