JP2018534819A5 - - Google Patents

Download PDF

Info

Publication number
JP2018534819A5
JP2018534819A5 JP2018515039A JP2018515039A JP2018534819A5 JP 2018534819 A5 JP2018534819 A5 JP 2018534819A5 JP 2018515039 A JP2018515039 A JP 2018515039A JP 2018515039 A JP2018515039 A JP 2018515039A JP 2018534819 A5 JP2018534819 A5 JP 2018534819A5
Authority
JP
Japan
Prior art keywords
data input
logic state
input signal
signal
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018515039A
Other languages
English (en)
Japanese (ja)
Other versions
JP7159044B2 (ja
JP2018534819A (ja
Filing date
Publication date
Priority claimed from US14/863,710 external-priority patent/US9467143B1/en
Application filed filed Critical
Publication of JP2018534819A publication Critical patent/JP2018534819A/ja
Publication of JP2018534819A5 publication Critical patent/JP2018534819A5/ja
Application granted granted Critical
Publication of JP7159044B2 publication Critical patent/JP7159044B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2018515039A 2015-09-24 2016-09-09 データ電圧レベルに従ってデータをバッファリングするための反比例電圧－遅延バッファ Active JP7159044B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/863,710 2015-09-24
US14/863,710 US9467143B1 (en) 2015-09-24 2015-09-24 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
PCT/US2016/051073 WO2017053090A1 (en) 2015-09-24 2016-09-09 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Publications (3)

Publication Number Publication Date
JP2018534819A JP2018534819A (ja) 2018-11-22
JP2018534819A5 true JP2018534819A5 (enExample) 2019-10-03
JP7159044B2 JP7159044B2 (ja) 2022-10-24

Family

ID=57046514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018515039A Active JP7159044B2 (ja) 2015-09-24 2016-09-09 データ電圧レベルに従ってデータをバッファリングするための反比例電圧－遅延バッファ

Country Status (7)

Country Link
US (2) US9467143B1 (enExample)
EP (1) EP3353894A1 (enExample)
JP (1) JP7159044B2 (enExample)
KR (1) KR102604585B1 (enExample)
CN (1) CN108141213B (enExample)
BR (1) BR112018005973B1 (enExample)
WO (1) WO2017053090A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
US10796729B2 (en) * 2019-02-05 2020-10-06 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US10979049B2 (en) * 2019-05-03 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Logic buffer circuit and method
US11349458B1 (en) * 2021-09-22 2022-05-31 Microsoft Technology Licensing, Llc Transistor aging monitor circuit for increased stress-based aging compensation precision, and related methods

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532315B2 (enExample) * 1972-10-18 1978-01-26
US4700089A (en) * 1984-08-23 1987-10-13 Fujitsu Limited Delay circuit for gate-array LSI
JPH0834418B2 (ja) * 1984-08-23 1996-03-29 富士通株式会社 遅延回路
JPH07107978B2 (ja) 1985-11-07 1995-11-15 ロ−ム株式会社 Ｃ−ｍｏｓ回路
KR900008436B1 (ko) 1987-12-08 1990-11-20 삼성반도체통신 주식회사 듀얼 슬로프 파형 발생회로
US5151622A (en) * 1990-11-06 1992-09-29 Vitelic Corporation CMOS logic circuit with output coupled to multiple feedback paths and associated method
US5120992A (en) * 1991-07-03 1992-06-09 National Semiconductor Corporation CMOS output driver with transition time control circuit
JPH05191232A (ja) * 1992-01-08 1993-07-30 Oki Micro Design Miyazaki:Kk 遅延回路
JPH05218828A (ja) * 1992-02-04 1993-08-27 Hitachi Ltd 遅延回路
US5376848A (en) * 1993-04-05 1994-12-27 Motorola, Inc. Delay matching circuit
US5903169A (en) * 1996-07-24 1999-05-11 Lg Semicon Co., Ltd. Charge recycling differential logic (CRDL) circuit and storage elements and devices using the same
US6084430A (en) * 1997-12-31 2000-07-04 Intel Corporation Input buffer for a mixed voltage environment
US6031393A (en) 1997-12-31 2000-02-29 Intel Corporation Pass gate input buffer for a mixed voltage environment
US6236237B1 (en) 1998-02-27 2001-05-22 Altera Corporation Output buffer predriver with edge compensation
KR100297715B1 (ko) * 1998-09-01 2001-08-07 윤종용 출력버퍼제어회로및출력제어신호발생방법
US6150862A (en) 1998-10-15 2000-11-21 Intel Corporation Stable delay buffer
US6198308B1 (en) 1999-03-30 2001-03-06 Fairchild Semiconductor Corp. Circuit for dynamic switching of a buffer threshold
US6292041B1 (en) * 2000-02-16 2001-09-18 Hewlett Packard Company Circuit and method for limiting subthreshold leakage
JP2001256785A (ja) * 2000-03-13 2001-09-21 Toshiba Corp クロックバッファ回路およびこのクロックバッファ回路を有するインタフェースならびに同期型半導体記憶装置
JP2002009606A (ja) * 2000-06-27 2002-01-11 Nec Corp 半導体回路
US7098694B2 (en) 2004-11-12 2006-08-29 Agere Systems Inc. Overvoltage tolerant input buffer
US7562271B2 (en) * 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
KR100632626B1 (ko) * 2005-10-14 2006-10-09 주식회사 하이닉스반도체 데이터 입출력 동작시 소비 전류를 감소시키는 클럭 제어회로와 이를 포함하는 반도체 메모리 장치 및 그 데이터입출력 동작 방법
US7405606B2 (en) * 2006-04-03 2008-07-29 Intellectual Ventures Fund 27 Llc D flip-flop
KR101197272B1 (ko) 2009-10-30 2012-11-05 에스케이하이닉스 주식회사 데이터출력회로
TWI445310B (zh) * 2010-12-27 2014-07-11 Au Optronics Corp 移位暫存器
WO2011157109A2 (zh) * 2011-05-30 2011-12-22 华为技术有限公司 一种i/o电路和集成电路
KR20130042244A (ko) 2011-10-18 2013-04-26 에스케이하이닉스 주식회사 신호 전달 회로 및 이를 포함하는 플립플롭 회로
US8872570B2 (en) * 2012-12-28 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple power domain circuit and related method
KR20150080098A (ko) * 2013-12-30 2015-07-09 에스케이하이닉스 주식회사 반도체 장치
JP2015177347A (ja) * 2014-03-14 2015-10-05 株式会社東芝 レベルシフト回路
US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Similar Documents

Publication Publication Date Title
JP6158277B2 (ja) 交差結合効果を低減するためのシステムおよび方法
US9680472B2 (en) Voltage level shifter circuit
JP2016527654A5 (enExample)
JP2018534819A5 (enExample)
US20160119024A1 (en) Apparatus and method for digitally cancelling crosstalk
US9634670B2 (en) Frequency divider and related electronic device
US8928354B2 (en) Clock-delayed domino logic circuit and devices including the same
JP2019510332A5 (enExample)
JP7159044B2 (ja) データ電圧レベルに従ってデータをバッファリングするための反比例電圧－遅延バッファ
US9571076B2 (en) Bidirectional delay circuit and integrated circuit including the same
TWI568176B (zh) 電子裝置
CN105027438B (zh) 低泄漏保留寄存器盘
CN105703761B (zh) 输入/输出驱动电路
KR102697334B1 (ko) 클럭 스위치 장치 및 이를 포함하는 시스템-온-칩
US9165661B2 (en) Systems and methods for switching between voltages
JP2018526901A5 (enExample)
KR20120140013A (ko) 펄스 생성기
US20150008970A1 (en) Period signal generation circuit
US8981828B2 (en) Multi-phase generator
KR102401264B1 (ko) 양방향 지연 회로 및 이를 포함하는 집적 회로
US9419659B2 (en) Signal receiver, related method, and related electronic device