KR102604585B1 - 데이터 전압 레벨들에 따라 데이터를 버퍼링하기 위한 반비례 전압-지연 버퍼들 - Google Patents

데이터 전압 레벨들에 따라 데이터를 버퍼링하기 위한 반비례 전압-지연 버퍼들 Download PDF

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KR102604585B1
KR102604585B1 KR1020187011520A KR20187011520A KR102604585B1 KR 102604585 B1 KR102604585 B1 KR 102604585B1 KR 1020187011520 A KR1020187011520 A KR 1020187011520A KR 20187011520 A KR20187011520 A KR 20187011520A KR 102604585 B1 KR102604585 B1 KR 102604585B1
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logic state
data input
input signal
signal
control signal
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KR20180058793A (ko
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조슈아 랜스 퍼켓
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퀄컴 인코포레이티드
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
KR1020187011520A 2015-09-24 2016-09-09 데이터 전압 레벨들에 따라 데이터를 버퍼링하기 위한 반비례 전압-지연 버퍼들 Active KR102604585B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/863,710 2015-09-24
US14/863,710 US9467143B1 (en) 2015-09-24 2015-09-24 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
PCT/US2016/051073 WO2017053090A1 (en) 2015-09-24 2016-09-09 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

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KR20180058793A KR20180058793A (ko) 2018-06-01
KR102604585B1 true KR102604585B1 (ko) 2023-11-20

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US (2) US9467143B1 (enExample)
EP (1) EP3353894A1 (enExample)
JP (1) JP7159044B2 (enExample)
KR (1) KR102604585B1 (enExample)
CN (1) CN108141213B (enExample)
BR (1) BR112018005973B1 (enExample)
WO (1) WO2017053090A1 (enExample)

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* Cited by examiner, † Cited by third party
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US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
US10796729B2 (en) * 2019-02-05 2020-10-06 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US10979049B2 (en) * 2019-05-03 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Logic buffer circuit and method
US11349458B1 (en) * 2021-09-22 2022-05-31 Microsoft Technology Licensing, Llc Transistor aging monitor circuit for increased stress-based aging compensation precision, and related methods

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KR100297715B1 (ko) * 1998-09-01 2001-08-07 윤종용 출력버퍼제어회로및출력제어신호발생방법
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KR100632626B1 (ko) * 2005-10-14 2006-10-09 주식회사 하이닉스반도체 데이터 입출력 동작시 소비 전류를 감소시키는 클럭 제어회로와 이를 포함하는 반도체 메모리 장치 및 그 데이터입출력 동작 방법
US7405606B2 (en) * 2006-04-03 2008-07-29 Intellectual Ventures Fund 27 Llc D flip-flop
TWI445310B (zh) * 2010-12-27 2014-07-11 Au Optronics Corp 移位暫存器
WO2011157109A2 (zh) * 2011-05-30 2011-12-22 华为技术有限公司 一种i/o电路和集成电路
KR20130042244A (ko) 2011-10-18 2013-04-26 에스케이하이닉스 주식회사 신호 전달 회로 및 이를 포함하는 플립플롭 회로
US8872570B2 (en) * 2012-12-28 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple power domain circuit and related method
KR20150080098A (ko) * 2013-12-30 2015-07-09 에스케이하이닉스 주식회사 반도체 장치
JP2015177347A (ja) * 2014-03-14 2015-10-05 株式会社東芝 レベルシフト回路
US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001256785A (ja) * 2000-03-13 2001-09-21 Toshiba Corp クロックバッファ回路およびこのクロックバッファ回路を有するインタフェースならびに同期型半導体記憶装置
US20110102024A1 (en) 2009-10-30 2011-05-05 Hynix Semiconductor Inc. Data output circuit

Also Published As

Publication number Publication date
JP7159044B2 (ja) 2022-10-24
KR20180058793A (ko) 2018-06-01
CN108141213A (zh) 2018-06-08
BR112018005973B1 (pt) 2023-04-25
US9467143B1 (en) 2016-10-11
US9667250B2 (en) 2017-05-30
WO2017053090A1 (en) 2017-03-30
BR112018005973A2 (pt) 2018-10-16
EP3353894A1 (en) 2018-08-01
JP2018534819A (ja) 2018-11-22
US20170093397A1 (en) 2017-03-30
CN108141213B (zh) 2021-07-09

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