WO2011157109A2 - 一种i/o电路和集成电路 - Google Patents

一种i/o电路和集成电路 Download PDF

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Publication number
WO2011157109A2
WO2011157109A2 PCT/CN2011/074882 CN2011074882W WO2011157109A2 WO 2011157109 A2 WO2011157109 A2 WO 2011157109A2 CN 2011074882 W CN2011074882 W CN 2011074882W WO 2011157109 A2 WO2011157109 A2 WO 2011157109A2
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WIPO (PCT)
Prior art keywords
port
path
transistor
boosting module
gate
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PCT/CN2011/074882
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English (en)
French (fr)
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WO2011157109A3 (zh
Inventor
曹威
戴方明
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2011/074882 priority Critical patent/WO2011157109A2/zh
Priority to CN2011800006905A priority patent/CN102204105B/zh
Publication of WO2011157109A2 publication Critical patent/WO2011157109A2/zh
Publication of WO2011157109A3 publication Critical patent/WO2011157109A3/zh
Priority to US13/483,877 priority patent/US20120306561A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to an I/O circuit and an integrated circuit.
  • the I/O (Input and Output) circuit is indispensable for the chip. It acts as a transmission signal, power supply, and ESD (Electro-Static discharge) protection throughout the chip. As chip functions continue to become more complex, chip sizes continue to expand, and power requirements are higher, so the performance, power, and area requirements for chip I/O circuits are increasing.
  • FIG. 1 there is a prior art I/O circuit structure diagram.
  • the control signals Net P and Net N for controlling the PMOS driving transistor and the NMOS driving transistor are respectively from the same port of the boosting module (both in FIG. 1 are from the inverting port ON).
  • the control signals Net P and Net N respectively control the operation of the PMOS driving transistor and the NMOS driving transistor through two structurally symmetric paths.
  • the envelope relationship between the control signals Net P and Net N of the I/O circuit shown in Figure 1 is shown in Figure 2 and Figure 3.
  • control signals Net P and Net N are from the same port of the boosting module, and the two completely symmetrical paths are used to control the operation of the PMOS driving transistor and the NMOS driving transistor,
  • the control signals Net P and Net N are basically coincident (as shown in Figure 2;), and even the wrong envelope relationship (such as the Net N envelope Net P shown in Figure 3).
  • the error envelope relationship between the control signals Net P and Net N generated by the existing I/O circuit is the Delay Time and Transition Time of the final output signal, that is, the level is high to low or The time that the low-to-high flipping takes place has a great influence, which further affects the quality of the output signal. More seriously, since the PMOS and NMOS are used as the drive tubes of the I/O circuit, the size itself is large, so the control signal Net P and Net N generates a particularly large leakage current between Power and Ground during the flipping process, which poses a potential threat to the reliability of the entire chip.
  • an object of the present invention to provide an I/O circuit and an integrated circuit capable of generating a relationship between a PMOS drive transistor control signal envelope and an NMOS drive transistor control signal.
  • An embodiment of the present invention provides an I/O circuit, where the circuit includes: a boosting module, a P path, an N path, a PMOS driving tube, and an NMOS driving tube;
  • a rising edge of an output signal of the positive phase port of the boosting module is slower than a falling edge
  • a gate of the PMOS driving transistor is connected to a positive phase port of the boosting module through a P path;
  • a gate of the NMOS driving transistor is connected to an inverting port of the boosting module through an N path;
  • the P path includes an odd number of inverters connected in series in sequence; the N path envelopes an even number of inverters connected in series.
  • Embodiments of the present invention also provide an integrated circuit, the integrated circuit including the I/O circuit.
  • An embodiment of the present invention further provides an I/O circuit, where the circuit includes: a boost module, a P path,
  • N-channel, PMOS driver tube, and NMOS driver tube N-channel, PMOS driver tube, and NMOS driver tube
  • a falling edge of an output signal of the positive phase port of the boosting module is slower than a rising edge
  • a gate of the PMOS driving transistor is connected to an inverting port of the boosting module through a P path;
  • a gate of the NMOS driving transistor is connected to a positive phase port of the boosting module through an N path;
  • the P path includes an even number of inverters connected in series in sequence; the N path envelopes are sequentially connected in series with an odd number of inverters.
  • Embodiments of the present invention also provide an integrated circuit, the integrated circuit including the I/O circuit. According to a specific embodiment provided by the present invention, the present invention discloses the following technical effects:
  • the gate of the PMOS driving tube and the gate of the NMOS driving tube are designed to pass through the P path and the N path respectively.
  • the different phase ports of the boosting module are such that the control signal Net P for controlling the PMOS driving tube and the control signal Net N for controlling the NMOS driving tube are respectively from the positive and negative ports of the boosting module;
  • the number of stages of the inverters on the P path and the N path has a difference in the number of parity, so that the I/O circuit according to the embodiment of the present invention can generate a significant control signal of the PMOS driver tube, the Net P envelope NMOS driver.
  • FIG. 1 is a structural diagram of a prior art I/O circuit
  • FIG. 2 is a first envelope relationship diagram of control signals Net P and Net N of the I/O circuit shown in FIG. 1;
  • FIG. 3 is a second control signal Net P and Net N of the I/O circuit shown in FIG.
  • FIG. 4 is a structural diagram of an I/O circuit according to Embodiment 1 of the present invention;
  • FIG. 5 is a circuit structural diagram of a boosting module according to an embodiment of the present invention.
  • FIG. 6 is a waveform diagram of an input signal received by a boosting module and an output signal of a non-phase port according to an embodiment of the present invention
  • FIG. 7 is a waveform diagram of signals respectively outputted by a positive phase port and an inverting port of a boost module according to an embodiment of the present invention.
  • FIG. 8 is an envelope relationship diagram of control signals Net P and Net N of an I/O circuit according to an embodiment of the present invention
  • FIG. 9 is a structural diagram of an I/O circuit according to Embodiment 2 of the present invention.
  • FIG. 10 is a structural diagram of an I/O circuit according to Embodiment 3 of the present invention.
  • FIG. 11 is a structural diagram of an I/O circuit according to Embodiment 4 of the present invention.
  • an object of the present invention to provide an I/O circuit and an integrated circuit capable of generating a relationship between a PMOS drive transistor control signal envelope and an NMOS drive transistor control signal.
  • the I/O circuit includes a boosting module 10, a P path 20, an N path 30, a PMOS driving transistor 40, and an NMOS driving transistor 50.
  • the input port IN of the boosting module 10 is used as the input terminal Input of the I/O circuit, and the positive phase port OP of the boosting module 10 is connected to the gate of the PMOS driving tube 40 through the P path 20, The inverting port ON of the boosting module 10 is connected to the gate of the NMOS driving transistor 50 through the N path 30.
  • the source of the PMOS driving transistor 40 is connected to the operating power source Power; the source of the NMOS driving transistor 50 is grounded to the ground; the drain of the PMOS driving transistor 40 and the drain of the NMOS driving transistor 50 are shorted together.
  • the output of the I/O circuit is Output.
  • the P path 20 includes an odd number of inverters, and the odd number of inverters In series, they form a series branch. Specifically, in the series branch, an output end of the previous stage inverter is connected to an input end of the second stage inverter, and an input end of the first stage inverter is connected to the normal phase port OP of the boost module 10. The output of the last stage inverter is connected to the gate of the PMOS driving transistor 40.
  • the N-channel 30 includes an even number of inverters, and the even-numbered inverters are also connected in series to form a series branch. Specifically, in the series branch, an output end of the previous stage inverter is connected to an input end of the second stage inverter, and an input end of the first stage inverter is connected to the inversion port of the boost module 10 The output of the last stage inverter is connected to the gate of the NMOS drive transistor 50.
  • the boosting module 10 has the following waveform feature: the rising edge of the output signal of the positive phase port of the boosting module 10 is slower than the falling edge.
  • the gate of the PMOS driving transistor 40 and the gate of the NMOS driving transistor 50 are designed to be connected to the boosting module 10 through the P path 20 and the N path 30, respectively.
  • the positive phase port OP and the inverting port ON are such that the control signal Net P for controlling the PMOS driving transistor 40 and the control signal Net N for controlling the NMOS driving transistor 50 are respectively derived from the positive and negative terminals of the boosting module 10;
  • the I/O circuit can generate the control of the PMOS drive tube 40.
  • the signal Net P envelopes the relationship of the control signal Net N of the NMOS drive transistor 50.
  • the P path 20 includes three inverters, and the N path 30 includes two inverters as an example for description.
  • the P path 20 includes: a first inverter P1, a second inverter P2, and a third inverter P3.
  • the N path 30 includes: a fourth inverter N1, a fifth Inverter N2.
  • the input end of the first inverter P1 is connected to the positive phase port OP of the boosting module 10, and the output end of the first inverter P1 is connected to the input end of the second inverter P2;
  • An output end of the second inverter P2 is connected to an input end of the third inverter P3; an output end of the third inverter P3 is connected to a gate of the PMOS driving tube 40.
  • the input end of the fourth inverter N1 is connected to the inverting port ON of the boosting module 10, and the output end of the fourth inverter N1 is connected to the input end of the fifth inverter N2;
  • the output terminal of the fifth inverter N2 is connected to the gate of the NMOS driving transistor 50.
  • the P path 20 includes an odd number of inverters
  • the N path 30 includes A plurality of inverters can be used, and the number of inverters respectively included in the two paths can be specifically set according to the needs of the actual application.
  • the selection of the boosting module 10 in the I/O circuit is based on the principle that the area is as small as possible and the structure is as simple as possible under the premise of ensuring the function.
  • Figure 5 shows the structure of a commonly used boost module.
  • the boosting module 10 includes: a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M3, a second NMOS transistor M4, and a sixth inverter T1.
  • the source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are short-circuited together with a high-voltage power supply VDDPST (such as 3.3V, etc.).
  • VDDPST such as 3.3V, etc.
  • the drain of the first PMOS transistor M1 and the gate of the second PMOS transistor M2 are short-circuited as the inverting port ON of the boosting module 10.
  • the drain of the second PMOS transistor M2 and the gate of the first PMOS transistor M1 are short-circuited as the positive phase port OP of the boosting module 10.
  • the drain of the first NMOS transistor M3 is connected to the inverting port ON of the boosting module 10; the drain of the second NMOS transistor M4 is connected to the positive phase port OP of the boosting module 10.
  • the source of the first NMOS transistor M3 and the source of the second NMOS transistor M4 are short-circuited together with the ground VSSPST.
  • the gate of the first NMOS transistor M3 is connected to the input end of the sixth inverter T1, and the output terminal of the sixth inverter T1 is connected to the gate of the second NMOS transistor M4.
  • the power port of the sixth inverter T1 is connected to a low voltage power supply VDD (such as 1.1V, etc.) and a ground VSS.
  • VDD low voltage power supply
  • VSS ground voltage power supply
  • the positive phase port OP and the inverting port ON of the boosting module 10 are both based on the input port IN, that is, the positive phase port OP of the boosting module 10 is used to output the input received with the input port IN.
  • the signal is in phase with the same phase, and the inverting port ON is used to output a signal that is inverted from the input signal received by the input port IN.
  • the boost module 10 shown in Figure 5 is for avoiding output A step is generated on the falling edge of the signal to affect the signal quality.
  • the size of the first NMOS transistor M3 and the second NMOS transistor M4 may be larger than the size of the first PMOS transistor M1 and the second PMOS transistor M2.
  • the first NMOS may be set.
  • the size of the tube M3 and the second NMOS transistor M4 is approximately 10 times the size of the first PMOS transistor M1 and the second PMOS transistor M2.
  • the output signal output of the positive phase port OP of the boosting module 10 has the following characteristics: the rising edge of the output signal output is slower than the falling edge, that is, as shown in FIG. 6, the output signal output is low.
  • the rise time at which the level rises to a high level is significantly greater than the fall time from a high level to a low level.
  • the abscissa of the waveform shown in FIG. 6 is time, and the ordinate is voltage; the input shown in FIG. 6 is an input signal received by the boosting module 10.
  • the signal of the P path 20 is taken from the positive phase port OP of the boosting module 10, and the gate of the PMOS driving transistor 40 is controlled by an odd-numbered (eg, three-stage) inverter;
  • the signal of 30 is taken from the inverting port ON of the boosting module 10, and is controlled by an even-numbered (eg, two-stage) inverter to control the gate of the NMOS driving transistor 50; the boosting module 10 shown in FIG. 6 and FIG.
  • the input signal and the characteristics of the signals output by the two ports respectively can be obtained as shown in FIG. 8 by the relationship between the control signal Net P of the PMOS driver tube 40 and the control signal Net N of the NMOS driver tube 50.
  • the input signal input is boosted by the boosting module 10, and is output by the normal phase port OP and the inverting port ON, respectively, and the rising edge of the output waveform of the OP port is slower than The falling edge of the output signal of the ON port, the rising edge of the output signal of the ON port is slower than the falling edge of the output signal of the OP port, so the OP port output signal passes through the odd-numbered (eg, three-stage) inverter of the P path 20, and the output signal of the ON port After the even-numbered (eg, two-stage) inverter of the N-channel 30, it will produce the form of the apparent Net P envelope Net N as shown in Figure 8, which is the correct envelope relationship and conforms to the I/O circuit. Demand.
  • the I/O circuit based on the structure of the conventional I/O circuit, takes into account the waveform characteristics of the boosting module 10, and generates a significant control signal of the PMOS driving tube 40 by designing the two paths.
  • the Net P envelopes the relationship of the control signal Net N of the NMOS drive transistor 50, and the degree of its envelope can be adjusted by adjusting the size of the booster module 10 and the inverters included in the two paths.
  • the I/O circuit truly realizes that the envelope relationship can be adjusted according to actual needs, and There is no need to consider the relationship between the envelope relationship, the final output signal Delay Time, the Transition Time, the I/O circuit operating frequency, and the ability to properly drive the drive tube in the I/O circuit.
  • the I/O circuit of the embodiment of the invention effectively reduces the leakage current between the power source and the ground during the signal inversion process, and has the advantages that the Delay Time and the Transition Time of the final output signal are relatively easy to adjust, thereby ensuring the The quality of the final output signal meets the needs of the entire chip for high quality transmission signals.
  • the P path and the N path are respectively connected to the positive and negative ports of the same boosting module.
  • the P path and the N path may also be respectively connected to different positive boosting modules. , inverting port. It is only necessary to ensure that the different boosting modules receive the same input signal, the gate of the PMOS driving transistor is connected to the positive phase port of one of the boosting modules via an odd number of inverters, and the gate of the NMOS driving transistor is passed through an even number of inverters. Connect to the inverting port of one of the boost modules.
  • the circuit shown in the second embodiment differs from the first embodiment in that: the boosting module 10 of the I/O circuit includes two boosting submodules, which are respectively a first boosting submodule 101 and a After the two boosting sub-modules 102 are short-circuited, the input terminals of the two boosting sub-modules are connected together with the input signal Input.
  • the boosting module 10 of the I/O circuit includes two boosting submodules, which are respectively a first boosting submodule 101 and a After the two boosting sub-modules 102 are short-circuited, the input terminals of the two boosting sub-modules are connected together with the input signal Input.
  • the positive phase port OP1 of the first boosting submodule 101 is connected to the input terminal of the P path 20 as the positive phase port OP of the boosting module 10.
  • the inverting port ON2 of the second boosting submodule 102 is connected to the input end of the N path 30 as an inverting port of the boosting module 10.
  • circuit shown in the second embodiment is the same as that in the first embodiment, and details are not described herein again.
  • each boosting submodule The structure, function and working principle of each boosting submodule are the same as those of the boosting module described in the first embodiment.
  • the boosting module 10 may further include a plurality of (not limited to two) boosting submodules, and only need to ensure that the input ports of the boosting submodules are shorted and connected together.
  • the signal can be.
  • the positive phase port of any one of the boosting submodules can be set as the positive phase port of the boosting module, and the P channel input terminal can be set, and any booster can be set.
  • the inverting port of the module acts as the inverting port of the boosting module and is connected to the input of the N path.
  • the embodiment of the present invention further provides an integrated circuit, and the integrated circuit may include the I/O circuit described in the foregoing Embodiments 1 and 2.
  • Integrated power The circuit can be a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit capable of generating two signals having an envelope relationship.
  • CMOS Complementary Metal Oxide Semiconductor
  • an obvious PMOS driving transistor control signal envelope NMOS can be realized. Drive tube control signal relationship.
  • the third embodiment of the present invention provides an I/O circuit structure, and can also implement PMOS driving tube control signal envelope NMOS driving tube control. The relationship of the signals.
  • FIG. 10 is a structural diagram of an I/O circuit according to a third embodiment of the present invention.
  • the I/O circuit includes: a boosting module 100, a P path 200, an N path 300, a PMOS driving tube 400, and an NMOS driving tube 500.
  • the input port IN of the boosting module 100 is used as an input terminal of the I/O circuit, and the inverting port ON of the boosting module 100 is connected to the gate of the PMOS driving tube 400 through the P path 200.
  • the positive phase port OP of the boost module 100 is connected to the gate of the NMOS drive transistor 500 through the N path 300.
  • the source of the PMOS driving tube 400 is connected to the working power source Power; the source of the NMOS driving tube 500 is grounded to the ground; the drain of the PMOS driving tube 400 and the drain of the NMOS driving tube 500 are short-circuited as a
  • the output of the I/O circuit is Output.
  • the P path 200 includes an even number of inverters, and the even number of inverters are sequentially connected in series to form a series branch. Specifically, in the series branch, an output end of the previous stage inverter is connected to an input end of the second stage inverter, and an input end of the first stage inverter is connected to the inversion port of the boost module 100. The output of the last stage inverter is connected to the gate of the PMOS driving transistor 400.
  • the N path 300 includes an odd number of inverters, and the odd number of inverters are also connected in series to form a series branch. Specifically, in the series branch, an output end of the previous stage inverter is connected to an input end of the second stage inverter, and an input end of the first stage inverter is connected to the normal phase port OP of the boost module 100. The output of the last stage inverter is connected to the gate of the NMOS drive transistor 500.
  • the boosting module 100 has the following waveform characteristics: the falling edge of the output signal of the positive phase port of the boosting module 100 is slower than the rising edge.
  • the gate of the PMOS driving tube 400 and the gate of the NMOS driving tube 500 are respectively connected to the boosting module 100 through the P path 200 and the N path 300.
  • the inverting port ON and the positive phase port OP are such that the control signal Net P for controlling the PMOS driving tube 400 and the control signal Net N for controlling the NMOS driving tube 500 are respectively from the positive and negative ports of the boosting module 100;
  • the I/O circuit of the embodiment of the present invention can be made to generate a significant control signal of the PMOS driving tube 400.
  • the P path 200 includes two inverters, and the N path 300 includes three inverters as an example. In practical applications, it is only necessary to ensure that the P path 200 includes an even number of inverters, and the N path 300 includes an odd number of inverters, and the number of inverters respectively included in the two paths may be according to actual application requirements. Specific settings.
  • the working principle of the I/O circuit in the third embodiment shown in FIG. 10 is similar to that in the first embodiment, and details are not described herein again.
  • the P path and the N path are respectively connected to the opposite and positive phase ports of the same boosting module.
  • the P path and the N path may also be respectively connected to different boosts.
  • the inverse and positive phase ports of the module It is only necessary to ensure that the different boosting modules receive the same input signal, the gate of the PMOS driving transistor is connected to the inverting port of one of the boosting modules via an even number of inverters, and the gate of the NMOS driving transistor passes through an odd number of inverters. Connect to the positive phase port of one of the boost modules.
  • FIG. 11 is a structural diagram of an I/O circuit according to a fourth embodiment of the present invention.
  • the circuit shown in the fourth embodiment differs from the third embodiment in that: the boosting module 100 of the I/O circuit includes two boosting submodules, which are respectively a third boosting submodule 1001 and a The four boost sub-module 1002, and the input ends of the two boost sub-modules are short-circuited, together with the input signal Input.
  • the positive phase port ON1 of the third boosting submodule 1001 is connected to the input end of the P path 200 as an inverting port ON of the boosting module 100.
  • the inverting port OP2 of the fourth boosting submodule 1002 is connected to the input terminal of the N path 300 as the positive phase port OP of the boosting module 100.
  • each boosting submodule The structure, function and working principle of each boosting submodule are the same as the boosting mode described in the third embodiment.
  • the blocks are the same.
  • the boosting module 100 may further include a plurality of (not limited to two) boosting submodules, and only need to ensure that the input ports of the boosting submodules are shorted and connected together.
  • the signal can be, in this case, the positive phase port of any one of the plurality of boost submodules can be set as the input port of the positive phase port of the boost module to the N path, and any boost can be set.
  • the inverting port of the submodule serves as the inverting port of the boosting module to the P path input.
  • the embodiment of the present invention further provides an integrated circuit, and the integrated circuit may include the I/O circuit according to the foregoing embodiments 3 and 4.
  • the integrated circuit can be a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit capable of generating two signals having an envelope relationship.
  • CMOS Complementary Metal Oxide Semiconductor

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Abstract

一种I/O电路，所述电路包括：升压模块、P通路、N通路、PMOS驱动管、以及NMOS驱动管；所述升压模块正相端口的输出信号的上升沿缓慢于下降沿；所述PMOS驱动管的栅极通过P通路接所述升压模块的正相端口；所述NMOS驱动管的栅极通过N通路接所述升压模块的反相端口；所述P通路包括依次串联的奇数个反相器；所述N通路包络依次串联的偶数个反相器。本发明还提供一种集成电路。采用本发明实施例，能够产生明显的PMOS驱动管控制信号包络NMOS驱动管控制信号的关系。

Description

一种 I/O电路和集成电路 技术领域
本发明涉及电子技术领域， 特别是涉及一种 I/O电路和集成电路。
背景技术
I/O ( Input and Output ) 电路对于芯片而言是不可缺少的， 它在整个芯片 中担任着传输信号、 供电和 ESD ( Electro-Static discharge, 静电释放）保护等 作用。 由于芯片功能不断趋于复杂化， 芯片规模不断扩大， 功耗要求也越来越 高， 所以对于芯片 I/O电路的性能、 功耗和面积方面的要求也越来越高。
参照图 1 , 为现有技术的 I/O电路结构图。 如图 1所示， 现有的 I/O电路 中， 控制 PMOS驱动管和 NMOS驱动管的控制信号 Net P和 Net N分别来自 于升压模块的同一端口 （图 1 中均来自反相端口 ON ), 该控制信号 Net P和 Net N分别通过两条结构对称的通路去控制 PMOS驱动管和 NMOS驱动管工 作。 图 1所示 I/O电路的控制信号 Net P和 Net N之间的包络关系有图 2和图 3所示两种情况。
由图 2和图 3可知， 现有技术中， 由于控制信号 Net P和 Net N来自升压 模块的同一端口， 且经过两条结构完全对称的通路分别去控制 PMOS驱动管 和 NMOS驱动管工作， 使得控制信号 Net P和 Net N基本上是重合的（如图 2 所示；)， 甚至于是错误的包络关系 （如图 3所示 Net N包络 Net P )。
现有 I/O电路产生的控制信号 Net P和 Net N之间的错误包络关系对最终 输出信号的 Delay Time (延迟时间 )和 Transition Time (翻转时间， 即为电平 由高到低或由低到高翻转所经历的时间）影响很大， 进一步影响输出信号的质 量； 更严重的， 由于 PMOS和 NMOS作为 I/O电路的驱动管， 其本身尺寸就 很大，所以控制信号 Net P和 Net N在翻转过程中会在 Power(电源）和 Ground (地）之间产生特别大的漏电流， 进而对整个芯片的可靠性产生潜在的威胁。
现有技术中，即使人为的调整升压模块以及两个通路上反相器的尺寸来实 现 Net P包络 Net N的关系， 但是该方法必须要考虑包络关系、 最终输出信号 的 Delay Time和 Transition Time, I/O电路工作频率以及能否正常驱动 I/O电 路的驱动管等因素之间的折中关系，使得实现较复杂且实现的包络关系效果也 不明显。
发明内容
有鉴于此， 本发明的目的在于提供一种 I/O电路和集成电路， 能够产生明 显的 PMOS驱动管控制信号包络 NMOS驱动管控制信号的关系。
本发明实施例提供一种 I/O电路， 所述电路包括： 升压模块、 P通路、 N 通路、 PMOS驱动管、 以及 NMOS驱动管；
所述升压模块正相端口的输出信号的上升沿緩慢于下降沿；
所述 PMOS驱动管的栅极通过 P通路接所述升压模块的正相端口； 所述 NMOS驱动管的栅极通过 N通路接所述升压模块的反相端口；
所述 P通路包括依次串联的奇数个反相器； 所述 N通路包络依次串联的 偶数个反相器。
本发明实施例还提供一种集成电路， 所述集成电路包括所述的 I/O电路。 本发明实施例还提供一种 I/O电路， 所述电路包括： 升压模块、 P通路、
N通路、 PMOS驱动管、 以及 NMOS驱动管；
所述升压模块正相端口的输出信号的下降沿緩慢于上升沿；
所述 PMOS驱动管的栅极通过 P通路接所述升压模块的反相端口； 所述
NMOS驱动管的栅极通过 N通路接所述升压模块的正相端口；
所述 P通路包括依次串联的偶数个反相器； 所述 N通路包络依次串联的 奇数个反相器。
本发明实施例还提供一种集成电路， 所述集成电路包括所述的 I/O电路。 根据本发明提供的具体实施例， 本发明公开了以下技术效果：
本发明实施例所述 I/O电路中，基于升压模块正相端口输出信号的波形特 点， 设计所述 PMOS驱动管的栅极和 NMOS驱动管的栅极分别通过 P通路和 N通路接所述升压模块的不同相端口， 使得控制所述 PMOS驱动管的控制信 号 Net P和控制所述 NMOS驱动管的控制信号 Net N分别来自升压模块的正反 两个端口； 同时， 通过设计使得 P通路和 N通路上的反相器的级数具有奇偶 个数的差别， 由此可以使得本发明实施例所述 I/O电路能够产生明显的 PMOS 驱动管的控制信号 Net P包络 NMOS驱动管的控制信号 Net N的关系。 附图说明
图 1为现有技术的 I/O电路结构图；
图 2为图 1所示 I/O电路的控制信号 Net P和 Net N的第一种包络关系图； 图 3为图 1所示 I/O电路的控制信号 Net P和 Net N的第二种包络关系图； 图 4为本发明实施例一的 I/O电路结构图；
图 5为本发明实施例的升压模块的电路结构图；
图 6 为本发明实施例的升压模块接收到的输入信号和正相端口的输出信 号的波形图；
图 7 为本发明实施例的升压模块的正相端口和反相端口分别输出的信号 的波形图；
图 8为本发明实施例的 I/O电路的控制信号 Net P和 Net N的包络关系图； 图 9为本发明实施例二的 I/O电路结构图；
图 10为本发明实施例三的 I/O电路结构图；
图 11为本发明实施例四的 I/O电路结构图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图和 具体实施方式对本发明作进一步详细的说明。
有鉴于此， 本发明的目的在于提供一种 I/O电路和集成电路， 能够产生明 显的 PMOS驱动管控制信号包络 NMOS驱动管控制信号的关系。
参照图 4, 为本发明实施例一的 I/O电路结构图。 如图 4所示， 所述 I/O 电路包括：升压模块 10、 P通路 20、 N通路 30、 PMOS驱动管 40、 以及 NMOS 驱动管 50。
其中， 所述升压模块 10的输入端口 IN作为所述 I/O电路的输入端 Input, 所述升压模块 10的正相端口 OP通过 P通路 20接 PMOS驱动管 40的栅极， 所述升压模块 10的反相端口 ON通过 N通路 30接 NMOS驱动管 50的栅极。
所述 PMOS驱动管 40的源极接工作电源 Power; 所述 NMOS驱动管 50 的源极接地 Ground;所述 PMOS驱动管 40的漏极和所述 NMOS驱动管 50的 漏极短接后作为所述 I/O电路的输出端 Output。
本发明实施例中， 所述 P通路 20包括奇数个反相器， 且该奇数个反相器 依次串联， 构成一串联支路。 具体的， 该串联支路中， 前一级反相器的输出端 接后一级反相器的输入端， 第一级反相器的输入端接所述升压模块 10的正相 端口 OP, 最后一级反相器的输出端接所述 PMOS驱动管 40的栅极。
所述 N通路 30包括偶数个反相器， 且该偶数个反相器也是依次串联， 构 成一串联支路。 具体的， 该串联支路中， 前一级反相器的输出端接后一级反相 器的输入端， 第一级反相器的输入端接所述升压模块 10的反相端口 ON, 最 后一级反相器的输出端接所述 NMOS驱动管 50的栅极。
需要说明的是， 本发明实施例一所述 I/O电路中， 所述升压模块 10具有 如下波形特征：该升压模块 10的正相端口的输出信号的上升沿緩慢于下降沿。
本发明实施例中， 基于升压模块 10的波形特点， 设计所述 PMOS驱动管 40的栅极和 NMOS驱动管 50的栅极分别通过 P通路 20和 N通路 30接所述 升压模块 10的正相端口 OP和反相端口 ON, 使得控制所述 PMOS驱动管 40 的控制信号 Net P和控制所述 NMOS驱动管 50的控制信号 Net N分别来自升 压模块 10的正反两个端口； 同时， 通过设计使得 P通路 20和 N通路 30上的 反相器的级数具有奇偶个数的差别， 由此可以使得本发明实施例所述 I/O电路 能够产生明显的 PMOS驱动管 40的控制信号 Net P包络 NMOS驱动管 50的 控制信号 Net N的关系。
如图 4所示， 本发明实施例中， 仅以 P通路 20包括三个反相器、 N通路 30包括两个反相器为例进行说明。
如图 4所示， 所述 P通路 20包括： 第一反相器 Pl、 第二反相器 P2、 第 三反相器 P3; 所述 N通路 30包括： 第四反相器 Nl、 第五反相器 N2。
其中， 所述第一反相器 P1的输入端接所述升压模块 10的正相端口 OP, 所述第一反相器 P1的输出端接所述第二反相器 P2的输入端；所述第二反相器 P2的输出端接所述第三反相器 P3的输入端； 所述第三反相器 P3的输出端接 所述 PMOS驱动管 40的栅极。
所述第四反相器 N1的输入端接所述升压模块 10的反相端口 ON,所述第 四反相器 N1 的输出端接所述第五反相器 N2的输入端； 所述第五反相器 N2 的输出端接所述 NMOS驱动管 50的栅极。
在实际应用中， 只需保证 P通路 20包括奇数个反相器、 N通路 30包括偶 数个反相器即可， 至于两个通路分别包括的反相器的个数， 可以根据实际应用 的需要具体设定。
在实际设计中， 由于受到 I/O电路面积的限制， I/O电路中升压模块 10的 选取是基于在保证功能的前提下， 面积尽可能的小、 结构尽可能筒单的原则。 图 5给出了一种常用的升压模块的结构示意图。
参照图 5, 为本发明实施例的升压模块的电路结构图。 如图 5所示， 所述 升压模块 10包括： 第一 PMOS管 Ml、 第二 PMOS管 M2、 第一 NMOS管 M3、 第二 NMOS管 M4、 第六反相器 Tl。
其中， 所述第一 PMOS管 Ml的源极和第二 PMOS管 M2的源极短接， 一同接高压电源 VDDPST (如 3.3V等）。
所述第一 PMOS管 Ml的漏极和所述第二 PMOS管 M2的栅极短接， 作 为所述升压模块 10的反相端口 ON。
所述第二 PMOS管 M2的漏极和所述第一 PMOS管 Ml的栅极短接， 作 为所述升压模块 10的正相端口 OP。
所述第一 NMOS管 M3的漏极接所述升压模块 10的反相端口 ON; 所述 第二 NMOS管 M4的漏极接所述升压模块 10的正相端口 OP。
所述第一 NMOS管 M3的源极和所述第二 NMOS管 M4的源极短接， 一 同接地 VSSPST。
所述第一 NMOS管 M3的栅极接所述第六反相器 T1的输入端，所述第六 反相器 T1的输出端接所述第二 NMOS管 M4的栅极。
所述第六反相器 T1的电源端口接低压电源 VDD (如 1.1V等）和地 VSS。 所述第一 NMOS管 M3的栅极与所述第六反相器 T1的公共端作为所述升 压模块 10的输入端口。
结合图 5,该升压模块 10的正相端口 OP和反相端口 ON均是基于输入端 口 IN的， 即为该升压模块 10的正相端口 OP用于输出与输入端口 IN接收到 的输入信号同相位的信号， 而反相端口 ON则用于输出与输入端口 IN接收到 的输入信号反相的信号。
参照图 6, 为本发明实施例一所述升压模块 10接收到的输入信号 input和 正相端口的输出信号 output的波形图。 图 5所示升压模块 10为了避免在输出 信号下降沿上产生台阶进而影响信号质量， 可以设定第一 NMOS管 M3和第 二 NMOS管 M4的尺寸大于第一 PMOS管 Ml和第二 PMOS管 M2的尺寸， 例如， 可以设定第一 NMOS管 M3和第二 NMOS管 M4的尺寸大约为第一 PMOS管 Ml和第二 PMOS管 M2的尺寸的 10倍左右。 由此使得， 升压模块 10的正相端口 OP的输出信号 output具有下述特性： 所述输出信号 output的 上升沿緩慢于下降沿， 也就是， 如图 6所示， 该输出信号 output由低电平上升 为高电平的上升时间明显大于其由高电平下降为低电平的下降时间。其中， 图 6所示波形的横坐标为时间， 纵坐标为电压； 图 6中所示 input为所述升压模 块 10接收到的输入信号。
则所述升压模块 10的正相端口 OP和反相端口 OP分别输出的信号的波形 如图 7所示。 两个端口分别输出的信号是反相的。
由于本发明实施例中，所述 P通路 20的信号取自升压模块 10的正相端口 OP, 经过奇数级（如三级）反相器去控制 PMOS驱动管 40的栅极； 而 N通 路 30的信号取自升压模块 10的反相端口 ON, 经过偶数级（如两级）反相器 去控制 NMOS驱动管 50的栅极； 结合图 6和图 7所示升压模块 10接收到的 输入信号和两个端口分别输出的信号的特性， 可以得到 PMOS驱动管 40的控 制信号 Net P与 NMOS驱动管 50的控制信号 Net N的包络关系如图 8所示。
结合图 6和图 7进行分析为： 如图 7所示， 输入信号 input经过升压模块 10升压后， 分别由正相端口 OP和反相端口 ON输出， OP端口输出波形的上 升沿緩慢于 ON端口输出信号的下降沿， ON端口输出信号的上升沿緩慢于 OP 端口输出信号的下降沿， 故而 OP端口输出信号经过 P通路 20的奇数级（如 三级）反相器、 ON端口输出信号经过 N通路 30的偶数级（如两级）反相器 后， 将会产生如图 8所示的明显的 Net P包络 Net N的形式， 这是正确的包络 关系， 符合 I/O电路的需求。
本发明实施例所述 I/O电路， 基于传统的 I/O电路的结构， 考虑到升压模 块 10的波形特性， 通过对两条通路的设计， 来产生明显的 PMOS驱动管 40 的控制信号 Net P包络 NMOS驱动管 50的控制信号 Net N的关系， 并且其包 络的程度可以通过调节升压模块 10和两条通路包括的反相器的尺寸来实现相 应的调节。 所述 I/O电路真正实现了包络关系可以根据实际需要进行调节， 并 且不用考虑包络关系、 最终输出信号的 Delay Time、 Transition Time、 I/O电路 工作频率以及能否正常驱动 I/O电路中的驱动管等因素之间的折中关系。
本发明实施例所述 I/O电路，有效地减小了在信号翻转过程中电源与地之 间的漏电流，并且具有最终输出信号的 Delay Time和 Transition Time比较容易 调节的优点， 进而保证了最终输出信号的质量， 满足整个芯片高质量传输信号 的需求。
本发明实施例一中， P通路和 N通路分别接同一升压模块的正、反相端口， 在本发明其他实施例中， 所述 P通路和 N通路也可以分别接不同升压模块的 正、 反相端口。 只需保证， 该不同的升压模块接收同一输入信号， PMOS驱动 管的栅极经奇数个反相器接其中一升压模块的正相端口且 NMOS驱动管的栅 极经偶数个反相器接其中一升压模块的反相端口即可。
参照图 9, 为本发明实施例二的 I/O电路结构图。 如图 9所示， 实施例二 所示电路与实施例一的区别在于： 所述 I/O电路的升压模块 10包括两个升压 子模块， 分别为第一升压子模块 101和第二升压子模块 102, 且两个升压子模 块的输入端短接后， 一同接输入信号 Input。
所述第一升压子模块 101的正相端口 OP1作为所述升压模块 10的正相端 口 OP接所述 P通路 20的输入端。
所述第二升压子模块 102的反相端口 ON2作为所述升压模块 10的反相端 口 ON接所述 N通路 30的输入端。
实施例二所示电路其余与实施例一相同， 在此不再赘述。
其中，各升压子模块的结构、功能与工作原理均与实施例一所述的升压模 块相同。
需要说明的是，本发明实施例中，所述升压模块 10还可以包括若干个（不 限于两个 )升压子模块， 只需保证各升压子模块的输入端口短接且一同接输入 信号即可， 此时， 可以设定若干个升压子模块中任一个升压子模块的正相端口 作为所述升压模块的正相端口接 P通路输入端，设定任一个升压子模块的反相 端口作为所述升压模块的反相端口接 N通路的输入端。
对应于本发明实施例一和二提供的 I/O电路，本发明实施例还提供一种集 成电路， 所述集成电路可以包括前述实施例一和二所述的 I/O电路。 该集成电 路可以为各种能够产生具有包络关系的两路信号的 CMOS ( Complementary Metal Oxide Semiconductor, 互补金属氧化物半导体） 集成电路。 本发明实施例一和二所述的 I/O电路， 当升压模块 10的正相端口的输出 信号的上升沿緩' ¾于下降沿时， 能够实现明显的 PMOS驱动管控制信号包络 NMOS 驱动管控制信号的关系。 而当升压模块正相端口的输出信号呈现下降 沿緩慢于上升沿的特性时， 本发明实施例三提供一种 I/O电路结构， 也能够实 现 PMOS驱动管控制信号包络 NMOS驱动管控制信号的关系。
参照图 10, 为本发明实施例三的 I/O电路结构图。如图 10所示， 所述 I/O 电路包括： 升压模块 100、 P通路 200、 N通路 300、 PMOS驱动管 400、 以及 NMOS驱动管 500。
其中，所述升压模块 100的输入端口 IN作为所述 I/O电路的输入端 Input, 所述升压模块 100的反相端口 ON通过 P通路 200接 PMOS驱动管 400的栅 极， 所述升压模块 100的正相端口 OP通过 N通路 300接 NMOS驱动管 500 的栅极。
所述 PMOS驱动管 400的源极接工作电源 Power;所述 NMOS驱动管 500 的源极接地 Ground; 所述 PMOS驱动管 400的漏极和所述 NMOS驱动管 500 的漏极短接后作为所述 I/O电路的输出端 Output。
本发明实施例中，所述 P通路 200包括偶数个反相器，且该偶数个反相器 依次串联， 构成一串联支路。 具体的， 该串联支路中， 前一级反相器的输出端 接后一级反相器的输入端，第一级反相器的输入端接所述升压模块 100的反相 端口 ON, 最后一级反相器的输出端接所述 PMOS驱动管 400的栅极。
所述 N通路 300包括奇数个反相器， 且该奇数个反相器也是依次串联， 构成一串联支路。 具体的， 该串联支路中， 前一级反相器的输出端接后一级反 相器的输入端， 第一级反相器的输入端接所述升压模块 100的正相端口 OP, 最后一级反相器的输出端接所述 NMOS驱动管 500的栅极。
需要说明的是， 本发明实施例三所述 I/O电路中， 所述升压模块 100具有 如下波形特征： 该升压模块 100 的正相端口的输出信号的下降沿緩慢于上升 沿。 本发明实施例中， 基于升压模块 100的波形特点， 设计所述 PMOS驱动 管 400的栅极和 NMOS驱动管 500的栅极分别通过 P通路 200和 N通路 300 接所述升压模块 100的反相端口 ON和正相端口 OP, 使得控制所述 PMOS驱 动管 400的控制信号 Net P和控制所述 NMOS驱动管 500的控制信号 Net N分 别来自升压模块 100的正反两个端口； 同时， 通过设计使得 P通路 200和 N 通路 300上的反相器的级数具有奇偶个数的差别，由此可以使得本发明实施例 所述 I/O电路能够产生明显的 PMOS驱动管 400的控制信号 Net P包络 NMOS 驱动管 500的控制信号 Net N的关系。
图 10中仅以 P通路 200包括两个反相器、 N通路 300包括三个反相器为 例进行说明。 在实际应用中， 只需保证 P通路 200包括偶数个反相器、 N通路 300包括奇数个反相器即可， 至于两个通路分别包括的反相器的个数， 可以根 据实际应用的需要具体设定。
图 10所示实施例三所述 I/O电路的工作原理与实施例一相似， 在此不再 赘述。
相应的， 本发明实施例三中， P通路和 N通路分别接同一升压模块的反、 正相端口， 在本发明其他实施例中， 所述 P通路和 N通路也可以分别接不同 升压模块的反、 正相端口。 只需保证， 该不同的升压模块接收同一输入信号， PMOS 驱动管的栅极经偶数个反相器接其中一升压模块的反相端口且 NMOS 驱动管的栅极经奇数个反相器接其中一升压模块的正相端口即可。
参照图 11 , 为本发明实施例四的 I/O电路结构图。 如图 11所示， 实施例 四所示电路与实施例三的区别在于： 所述 I/O电路的升压模块 100包括两个升 压子模块， 分别为第三升压子模块 1001和第四升压子模块 1002, 且两个升压 子模块的输入端短接后， 一同接输入信号 Input。
所述第三升压子模块 1001的正相端口 ON1作为所述升压模块 100的反相 端口 ON接所述 P通路 200的输入端。
所述第四升压子模块 1002的反相端口 OP2作为所述升压模块 100的正相 端口 OP接所述 N通路 300的输入端。
实施例四所示电路其余与实施例三相同， 在此不再赘述。
其中，各升压子模块的结构、功能与工作原理均与实施例三所述的升压模 块相同。
需要说明的是，本发明实施例中，所述升压模块 100还可以包括若干个（不 限于两个 )升压子模块， 只需保证各升压子模块的输入端口短接且一同接输入 信号即可， 此时， 可以设定若干个升压子模块中任一个升压子模块的正相端口 作为所述升压模块的正相端口接 N通路的输入端， 设定任一个升压子模块的 反相端口作为所述升压模块的反相端口接 P通路输入端。
对应于本发明实施例三和四提供的 I/O电路，本发明实施例还提供一种集 成电路， 所述集成电路可以包括前述实施例三和四所述的 I/O电路。 该集成电 路可以为各种能够产生具有包络关系的两路信号的 CMOS ( Complementary Metal Oxide Semiconductor, 互补金属氧化物半导体） 集成电路。
以上对本发明所提供的一种 I/O电路和集成电路， 进行了详细介绍， 本文 只是用于帮助理解本发明的方法及其核心思想； 同时，对于本领域的一般技术 人员， 依据本发明的思想， 在具体实施方式及应用范围上均会有改变之处。 综 上所述， 本说明书内容不应理解为对本发明的限制。

Claims

权 利 要 求
1、 一种 I/O 电路， 其特征在于， 所述电路包括： 升压模块、 P通路、 N 通路、 PMOS驱动管、 以及 NMOS驱动管；
所述升压模块正相端口的输出信号的上升沿緩慢于下降沿；
所述 PMOS驱动管的栅极通过 P通路接所述升压模块的正相端口； 所述
NMOS驱动管的栅极通过 N通路接所述升压模块的反相端口；
所述 P通路包括依次串联的奇数个反相器； 所述 N通路包络依次串联的 偶数个反相器。
2、 根据权利要求 1所述的 I/O电路， 其特征在于， 所述升压模块包括： 第一 PMOS管、 第二 PMOS管、 第一 NMOS管、 第二 NMOS管、 第六反相 哭口. ,
其中， 所述第一 PMOS管的源极和第二 PMOS管的源极短接， 一同接高 压电源；
所述第一 PMOS管的漏极和所述第二 PMOS管的栅极短接， 作为所述升 压模块的反相端口；
所述第二 PMOS管的漏极和所述第一 PMOS管的栅极短接， 作为所述升 压模块的正相端口；
所述第一 NMOS管的漏极接所述升压模块的反相端口； 所述第二 NMOS 管的漏极接所述升压模块的正相端口；
所述第一 NMOS管的源极和所述第二 NMOS管的源极短接， 一同接地； 所述第一 NMOS管的栅极接所述第六反相器的输入端， 所述第六反相器 的输出端接所述第二 NMOS管的栅极；
所述第一 NMOS管的栅极与所述第六反相器的公共端作为所述升压模块 的输入端口。
3、 根据权利要求 2所述的 I/O电路， 其特征在于， 所述第一 NMOS管和 第二 NMOS管的尺寸大于所述第一 PMOS管和第二 PMOS管的尺寸。
4、 根据权利要求 1至 3任一项所述的 I/O电路， 其特征在于， 所述升压 模块包括若干个升压子模块； 所述若干个升压子模块的输入端口短接；
任一升压子模块的正相端口作为所述升压模块的正相端口；
任一升压子模块的反相端口作为所述升压模块的反相端口。
5、 根据权利要求 1至 3任一项所述的 I/O电路， 其特征在于， 所述 P通 路包括的奇数个反相器， 前一级反相器的输出端接后一级反相器的输入端， 第 一级反相器的输入端接所述升压模块的正相端口，最后一级反相器的输出端接 所述 PMOS驱动管的栅极。
6、 根据权利要求 1至 3任一项所述的 I/O电路， 其特征在于， 所述 N通 路包括的偶数个反相器， 前一级反相器的输出端接后一级反相器的输入端， 第 一级反相器的输入端接所述升压模块的反相端口，最后一级反相器的输出端接 所述 NMOS驱动管的栅极。
7、 一种集成电路， 其特征在于， 所述集成电路包括如权利要求 1至 6任 一项所述的 I/O电路。
8、 一种 I/O 电路， 其特征在于， 所述电路包括： 升压模块、 P通路、 N 通路、 PMOS驱动管、 以及 NMOS驱动管；
所述升压模块正相端口的输出信号的下降沿緩慢于上升沿；
所述 PMOS驱动管的栅极通过 P通路接所述升压模块的反相端口； 所述
NMOS驱动管的栅极通过 N通路接所述升压模块的正相端口；
所述 P通路包括依次串联的偶数个反相器； 所述 N通路包络依次串联的 奇数个反相器。
9、 根据权利要求 8所述的 I/O电路， 其特征在于， 所述升压模块包括若 干个升压子模块；
所述若干个升压子模块的输入端口短接；
任一升压子模块的正相端口作为所述升压模块的正相端口；
任一升压子模块的反相端口作为所述升压模块的反相端口。
10、 根据权利要求 8或 9所述的 I/O电路， 其特征在于， 所述 P通路包括 的偶数个反相器， 前一级反相器的输出端接后一级反相器的输入端， 第一级反 相器的输入端接所述升压模块的反相端口， 最后一级反相器的输出端接所述 PMOS驱动管的栅极。
11、根据权利要求 8或 9所述的 I/O电路， 其特征在于， 所述 N通路包括 的奇数个反相器， 前一级反相器的输出端接后一级反相器的输入端， 第一级反 相器的输入端接所述升压模块的正相端口， 最后一级反相器的输出端接所述 NMOS驱动管的栅极。
12、 一种集成电路， 其特征在于， 所述集成电路包括如权利要求 8至 11 任一项所述的 I/O电路。
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