WO2011157109A3 - 一种i/o电路和集成电路 - Google Patents

一种i/o电路和集成电路 Download PDF

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Publication number
WO2011157109A3
WO2011157109A3 PCT/CN2011/074882 CN2011074882W WO2011157109A3 WO 2011157109 A3 WO2011157109 A3 WO 2011157109A3 CN 2011074882 W CN2011074882 W CN 2011074882W WO 2011157109 A3 WO2011157109 A3 WO 2011157109A3
Authority
WO
WIPO (PCT)
Prior art keywords
driving transistor
pathway
circuit
booster module
pmos
Prior art date
Application number
PCT/CN2011/074882
Other languages
English (en)
French (fr)
Other versions
WO2011157109A2 (zh
Inventor
曹威
戴方明
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN2011800006905A priority Critical patent/CN102204105B/zh
Priority to PCT/CN2011/074882 priority patent/WO2011157109A2/zh
Publication of WO2011157109A2 publication Critical patent/WO2011157109A2/zh
Publication of WO2011157109A3 publication Critical patent/WO2011157109A3/zh
Priority to US13/483,877 priority patent/US20120306561A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Conversion In General (AREA)

Abstract

一种I/O电路，所述电路包括：升压模块、P通路、N通路、PMOS驱动管、以及NMOS驱动管；所述升压模块正相端口的输出信号的上升沿缓慢于下降沿；所述PMOS驱动管的栅极通过P通路接所述升压模块的正相端口；所述NMOS驱动管的栅极通过N通路接所述升压模块的反相端口；所述P通路包括依次串联的奇数个反相器；所述N通路包络依次串联的偶数个反相器。本发明还提供一种集成电路。采用本发明实施例，能够产生明显的PMOS驱动管控制信号包络NMOS驱动管控制信号的关系。
PCT/CN2011/074882 2011-05-30 2011-05-30 一种i/o电路和集成电路 WO2011157109A2 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2011800006905A CN102204105B (zh) 2011-05-30 2011-05-30 一种i/o电路和集成电路
PCT/CN2011/074882 WO2011157109A2 (zh) 2011-05-30 2011-05-30 一种i/o电路和集成电路
US13/483,877 US20120306561A1 (en) 2011-05-30 2012-05-30 I/o circuit and integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/074882 WO2011157109A2 (zh) 2011-05-30 2011-05-30 一种i/o电路和集成电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/483,877 Continuation US20120306561A1 (en) 2011-05-30 2012-05-30 I/o circuit and integrated circuit

Publications (2)

Publication Number Publication Date
WO2011157109A2 WO2011157109A2 (zh) 2011-12-22
WO2011157109A3 true WO2011157109A3 (zh) 2012-02-16

Family

ID=44662794

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/074882 WO2011157109A2 (zh) 2011-05-30 2011-05-30 一种i/o电路和集成电路

Country Status (3)

Country Link
US (1) US20120306561A1 (zh)
CN (1) CN102204105B (zh)
WO (1) WO2011157109A2 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103546146B (zh) * 2013-09-24 2016-03-02 中国科学院微电子研究所 抗单粒子瞬态脉冲cmos电路
CN104638919A (zh) * 2013-11-14 2015-05-20 中芯国际集成电路制造(上海)有限公司 用于i/o接口的两级升压转换电路
CN103824551B (zh) * 2014-02-27 2016-06-01 上海和辉光电有限公司 一种栅极驱动电路及显示面板
US9467143B1 (en) * 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4518873A (en) * 1981-08-13 1985-05-21 Fujitsu Limited Buffer circuit for driving a C-MOS inverter
US5124590A (en) * 1991-08-12 1992-06-23 Advanced Micro Devices, Inc. CMOS tri-mode input buffer
US20040085114A1 (en) * 2002-11-04 2004-05-06 Lg Electronics Inc. Output driving circuit
CN1957531A (zh) * 2004-04-14 2007-05-02 高通股份有限公司 先断后通预驱动器和电平移位器
US7808294B1 (en) * 2007-10-15 2010-10-05 Netlogic Microsystems, Inc. Level shifter with balanced rise and fall times

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101252354B (zh) * 2008-03-21 2010-06-09 钰创科技股份有限公司 降低超越量的输出级电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4518873A (en) * 1981-08-13 1985-05-21 Fujitsu Limited Buffer circuit for driving a C-MOS inverter
US5124590A (en) * 1991-08-12 1992-06-23 Advanced Micro Devices, Inc. CMOS tri-mode input buffer
US20040085114A1 (en) * 2002-11-04 2004-05-06 Lg Electronics Inc. Output driving circuit
CN1957531A (zh) * 2004-04-14 2007-05-02 高通股份有限公司 先断后通预驱动器和电平移位器
US7808294B1 (en) * 2007-10-15 2010-10-05 Netlogic Microsystems, Inc. Level shifter with balanced rise and fall times

Also Published As

Publication number Publication date
WO2011157109A2 (zh) 2011-12-22
CN102204105A (zh) 2011-09-28
CN102204105B (zh) 2013-08-07
US20120306561A1 (en) 2012-12-06

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