CN108141213B - 用于根据数据电压电平缓冲数据的反比电压延迟缓冲器 - Google Patents

用于根据数据电压电平缓冲数据的反比电压延迟缓冲器 Download PDF

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Publication number
CN108141213B
CN108141213B CN201680054591.8A CN201680054591A CN108141213B CN 108141213 B CN108141213 B CN 108141213B CN 201680054591 A CN201680054591 A CN 201680054591A CN 108141213 B CN108141213 B CN 108141213B
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data input
input signal
logic state
signal
data
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CN108141213A (zh
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乔舒亚·兰斯·帕克特
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
CN201680054591.8A 2015-09-24 2016-09-09 用于根据数据电压电平缓冲数据的反比电压延迟缓冲器 Active CN108141213B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/863,710 US9467143B1 (en) 2015-09-24 2015-09-24 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
US14/863,710 2015-09-24
PCT/US2016/051073 WO2017053090A1 (en) 2015-09-24 2016-09-09 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

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CN108141213A CN108141213A (zh) 2018-06-08
CN108141213B true CN108141213B (zh) 2021-07-09

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US (2) US9467143B1 (enExample)
EP (1) EP3353894A1 (enExample)
JP (1) JP7159044B2 (enExample)
KR (1) KR102604585B1 (enExample)
CN (1) CN108141213B (enExample)
BR (1) BR112018005973B1 (enExample)
WO (1) WO2017053090A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11984187B2 (en) * 2019-02-05 2024-05-14 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
US10979049B2 (en) * 2019-05-03 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Logic buffer circuit and method
US11349458B1 (en) * 2021-09-22 2022-05-31 Microsoft Technology Licensing, Llc Transistor aging monitor circuit for increased stress-based aging compensation precision, and related methods

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CN102204105A (zh) * 2011-05-30 2011-09-28 华为技术有限公司 一种i/o电路和集成电路

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KR100297715B1 (ko) * 1998-09-01 2001-08-07 윤종용 출력버퍼제어회로및출력제어신호발생방법
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KR20130042244A (ko) 2011-10-18 2013-04-26 에스케이하이닉스 주식회사 신호 전달 회로 및 이를 포함하는 플립플롭 회로
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US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

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JPH0834418B2 (ja) * 1984-08-23 1996-03-29 富士通株式会社 遅延回路
JPH05191232A (ja) * 1992-01-08 1993-07-30 Oki Micro Design Miyazaki:Kk 遅延回路
CN102136245A (zh) * 2010-12-27 2011-07-27 友达光电股份有限公司 移位寄存器
CN102204105A (zh) * 2011-05-30 2011-09-28 华为技术有限公司 一种i/o电路和集成电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11984187B2 (en) * 2019-02-05 2024-05-14 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US12417790B2 (en) 2019-02-05 2025-09-16 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device

Also Published As

Publication number Publication date
JP2018534819A (ja) 2018-11-22
WO2017053090A1 (en) 2017-03-30
BR112018005973B1 (pt) 2023-04-25
EP3353894A1 (en) 2018-08-01
JP7159044B2 (ja) 2022-10-24
US20170093397A1 (en) 2017-03-30
KR102604585B1 (ko) 2023-11-20
CN108141213A (zh) 2018-06-08
BR112018005973A2 (pt) 2018-10-16
US9667250B2 (en) 2017-05-30
KR20180058793A (ko) 2018-06-01
US9467143B1 (en) 2016-10-11

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