BR112018005973B1 - Armazenadores de tensão-retardo inversamente proporcionais para armazenar dados de acordo com níveis de tensão de dados - Google Patents

Armazenadores de tensão-retardo inversamente proporcionais para armazenar dados de acordo com níveis de tensão de dados Download PDF

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Publication number
BR112018005973B1
BR112018005973B1 BR112018005973-0A BR112018005973A BR112018005973B1 BR 112018005973 B1 BR112018005973 B1 BR 112018005973B1 BR 112018005973 A BR112018005973 A BR 112018005973A BR 112018005973 B1 BR112018005973 B1 BR 112018005973B1
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BR
Brazil
Prior art keywords
signal
data
data input
input signal
logic state
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BR112018005973-0A
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English (en)
Portuguese (pt)
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BR112018005973A2 (pt
Inventor
Joshua Lance Puckett
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Qualcomm Incorporated
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Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018005973A2 publication Critical patent/BR112018005973A2/pt
Publication of BR112018005973B1 publication Critical patent/BR112018005973B1/pt

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
BR112018005973-0A 2015-09-24 2016-09-09 Armazenadores de tensão-retardo inversamente proporcionais para armazenar dados de acordo com níveis de tensão de dados BR112018005973B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/863,710 2015-09-24
US14/863,710 US9467143B1 (en) 2015-09-24 2015-09-24 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
PCT/US2016/051073 WO2017053090A1 (en) 2015-09-24 2016-09-09 Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Publications (2)

Publication Number Publication Date
BR112018005973A2 BR112018005973A2 (pt) 2018-10-16
BR112018005973B1 true BR112018005973B1 (pt) 2023-04-25

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BR112018005973-0A BR112018005973B1 (pt) 2015-09-24 2016-09-09 Armazenadores de tensão-retardo inversamente proporcionais para armazenar dados de acordo com níveis de tensão de dados

Country Status (7)

Country Link
US (2) US9467143B1 (enExample)
EP (1) EP3353894A1 (enExample)
JP (1) JP7159044B2 (enExample)
KR (1) KR102604585B1 (enExample)
CN (1) CN108141213B (enExample)
BR (1) BR112018005973B1 (enExample)
WO (1) WO2017053090A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
US10796729B2 (en) * 2019-02-05 2020-10-06 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US10979049B2 (en) * 2019-05-03 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Logic buffer circuit and method
US11349458B1 (en) * 2021-09-22 2022-05-31 Microsoft Technology Licensing, Llc Transistor aging monitor circuit for increased stress-based aging compensation precision, and related methods

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KR100297715B1 (ko) * 1998-09-01 2001-08-07 윤종용 출력버퍼제어회로및출력제어신호발생방법
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US9467143B1 (en) 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

Also Published As

Publication number Publication date
CN108141213B (zh) 2021-07-09
JP7159044B2 (ja) 2022-10-24
US9467143B1 (en) 2016-10-11
WO2017053090A1 (en) 2017-03-30
BR112018005973A2 (pt) 2018-10-16
US20170093397A1 (en) 2017-03-30
CN108141213A (zh) 2018-06-08
KR102604585B1 (ko) 2023-11-20
KR20180058793A (ko) 2018-06-01
US9667250B2 (en) 2017-05-30
EP3353894A1 (en) 2018-08-01
JP2018534819A (ja) 2018-11-22

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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