JP2018190788A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2018190788A JP2018190788A JP2017090251A JP2017090251A JP2018190788A JP 2018190788 A JP2018190788 A JP 2018190788A JP 2017090251 A JP2017090251 A JP 2017090251A JP 2017090251 A JP2017090251 A JP 2017090251A JP 2018190788 A JP2018190788 A JP 2018190788A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- insulating film
- semiconductor device
- electrode
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 195
- 239000000758 substrate Substances 0.000 claims abstract description 175
- 230000015654 memory Effects 0.000 claims abstract description 144
- 239000003990 capacitor Substances 0.000 claims description 157
- 239000004020 conductor Substances 0.000 claims description 51
- 238000000034 method Methods 0.000 abstract description 27
- 230000015572 biosynthetic process Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 description 54
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 238000012986 modification Methods 0.000 description 19
- 230000004048 modification Effects 0.000 description 19
- 238000000926 separation method Methods 0.000 description 19
- 238000005530 etching Methods 0.000 description 16
- 239000010410 layer Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 239000012535 impurity Substances 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000003860 storage Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000012447 hatching Effects 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- -1 Metal Oxide Nitride Chemical class 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】半導体基板1の主面の容量素子領域CRには、その主面から突出する複数のフィンFBがX方向に延在した状態でY方向に沿って配置されている。また、半導体基板1の主面の容量素子領域CRには、容量素子CDの複数の容量電極CE1,CE2が、複数のフィンFBに対して交差した状態でX方向に沿って交互に配置されている。フィンFBは、半導体基板1の不揮発性メモリのメモリセルアレイに配置されるフィンの形成工程時に形成される。また、容量電極CE1は、不揮発性メモリの制御ゲート電極の形成工程時に形成される。また、容量電極CE2は、不揮発性メモリのメモリゲート電極の形成工程時に形成される。
【選択図】図8
Description
<半導体チップのレイアウト構成例>
図1は、本実施の形態1における半導体チップ(半導体装置)CHPのレイアウト構成例を示す図である。本実施の形態1の半導体チップ(以下、単にチップという)CHPは、CPU100、RAM200、アナログ回路300、EEPROM400、フラッシュメモリ500およびI/O回路600を有する。CPU(Central Processing Unit)100は、中央演算処理装置とも呼ばれ、記憶装置から命令を読み出して解読し、それに基づいて多種多様な演算や制御を行なう。RAM(Random Access Memory)200は、記憶情報をランダムに、すなわち、随時記憶されている記憶情報を読み出したり、記憶情報を新たに書き込んだりすることができる。RAMとしては、例えば、スタティック回路を用いたSRAM(Static RAM)を用いる。アナログ回路300は、アナログ信号(時間的に連続して変化する電圧や電流の信号)を扱う回路であり、例えば増幅回路、変換回路、変調回路、発振回路および電源回路等を有する。
図2は図1のチップCHPのメモリセルアレイMRの要部平面図、図3は図2のメモリセルアレイMRのメモリセルMCの拡大平面図、図4は図2のX1−X1線の断面図、図5は図2のX2−X2線の断面図、図6は図2のY1−Y1線の断面図、図7は図2のY2−Y2線の断面図である。なお、X,Yは平面視で互いに交差(好適には直交)する2つの方向を示している。また、平面視とは、半導体基板1の主面に垂直な方向から視た場合を意味する。また、図2および図3は平面図であるが、理解を容易にするため制御ゲート電極CGにハッチングを付した。
図27〜図62は、本実施の形態の半導体装置の製造工程中における基板1の要部断面図である。なお、以下の断面図において、X1−X1、X2−X2、Y1−Y1、Y2−Y2、X3−X3、X4−X4、Y3−Y3およびY4−Y4の表示は、各製造工程中における図2のX1−X1線、X2−X2線、Y1−Y1線およびY2−Y2線と、図8のX3−X3線、X4−X4線、Y3−Y3線およびY4−Y4線とに相当する箇所の断面図を示している。
本実施の形態2の半導体装置の構造例について図63および図64を参照して説明する。図63の左側は本実施の形態2の半導体装置における図8のX4−X4線の断面図、図63の右側は図63の左側の領域A3の拡大断面図、図64の左側は本実施の形態2の半導体装置における図8のY4−Y4線の断面図、図64の右側は図64の左側の領域A4の拡大断面図である。なお、本実施の形態2の半導体装置において、図8のX3−X3線の断面図は図10と同じであり、図8のY3−Y3線の断面図は図12と同じである。また、本実施の形態2のメモリセルアレイMRの構造は、前記実施の形態1と同じである。また、図63および図64の右側の断面図では図面を見易くするため容量絶縁膜Ciのハッチングを省略した。
図71の左側は実施の形態2の半導体装置の変形例における図8のX4−X4線の断面図、図71の右側は図71の左側の領域A5の拡大断面図、図72の左側は実施の形態2の半導体装置の変形例における図8のY4−Y4線の断面図、図72の右側は図72の左側の領域A6の拡大断面図である。なお、この変形例において、図8のX3−X3線の断面図は図10と同じであり、図8のY3−Y3線の断面図は図12と同じである。また、この変形例のメモリセルアレイMRの構造は、前記実施の形態1と同じである。また、図71および図72の右側の断面図では図面を見易くするため容量絶縁膜Ciのハッチングを省略した。
本実施の形態3の半導体装置の構造例について図73〜図75を参照して説明する。図73の左側は本実施の形態3の半導体装置における図8のX4−X4線の断面図、図73の右側は図73の左側の領域A7の拡大断面図、図74の左側は本実施の形態3の半導体装置における図8のY3−Y3線の断面図、図74の右側は図74の左側の領域A8の拡大断面図である。また、図75は本実施の形態3の半導体装置における図8のY4−Y4線の断面図である。なお、本実施の形態3の半導体装置において、図8のX3−X3線の断面図は図10と同じである。また、本実施の形態3のメモリセルアレイMRの構造は、前記実施の形態1と同じである。また、図73および図74の右側の断面図では図面を見易くするため容量絶縁膜Ciのハッチングを省略した。
6 絶縁膜
7 絶縁膜
10 絶縁膜
FA,FB フィン
STI 分離部
T,TL 溝
MR メモリセルアレイ
MC メモリセル
CG 制御ゲート電極
MG メモリゲート電極
Gim ゲート絶縁膜
Git ゲート絶縁膜
MD ドレイン領域
MS ソース領域
CR 容量素子領域
CD 容量素子
CE1,CE2 容量電極
Ci 容量絶縁膜
ig 絶縁膜
CF1,CF2 導体膜
Claims (20)
- 半導体基板に配置されたメモリ領域と、
前記半導体基板に配置された容量素子領域と、
を備え、
前記メモリ領域のメモリセルは、
前記半導体基板の一部で形成され、前記半導体基板の主面から第1方向に突出し、第2方向に幅を有し、前記第2方向に交差する第3方向に延在し、前記第2方向に沿って配置された複数の第1突出部と、
前記第1突出部との間に第1ゲート絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1ゲート電極と、
前記第1突出部との間に第2ゲート絶縁膜を介して配置され、前記複数の第1ゲート電極の各々の側面に前記第2ゲート絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2ゲート電極と、
前記第2ゲート絶縁膜を介して互いに隣接する前記第1ゲート電極および前記第2ゲート電極を挟むように、前記第1突出部に設けられた第1半導体領域および第2半導体領域と、
を備え、
前記容量素子領域の容量素子は、
前記半導体基板の一部で形成され、前記半導体基板の主面から前記第1方向に突出し、前記第2方向に幅を有し、前記第3方向に延在し、前記第2方向に沿って配置された複数の第2突出部と、
前記第2突出部との間に絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1容量電極と、
前記第2突出部との間に容量絶縁膜を介して配置され、前記複数の第1容量電極の各々の側面に前記容量絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2容量電極と、
を備え、
前記第1ゲート電極と前記第1容量電極とは、第1導体膜で形成され、
前記第2ゲート電極と前記第2容量電極とは、第2導体膜で形成され、
前記複数の第2突出部の隣接間隔は、前記複数の第1突出部の隣接間隔より小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記複数の第2突出部の隣接間隔は、前記容量絶縁膜の厚さの3倍以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記複数の第1容量電極の隣接間隔は、前記複数の第1ゲート電極の隣接間隔より小さい、半導体装置。 - 請求項3記載の半導体装置において、
前記複数の第1容量電極の隣接間隔は、前記容量絶縁膜の厚さの3倍以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1容量電極の前記第3方向の幅が、前記第1ゲート電極の前記第3方向の幅より小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記複数の第2突出部の隣接間に配置された前記第2容量電極の前記第1方向の長さが、前記複数の第1突出部の隣接間に配置された前記第2ゲート電極の前記第1方向の長さより長い、半導体装置。 - 請求項6記載の半導体装置において、
前記複数の第2突出部の隣接間に配置された前記第1容量電極と、前記第1容量電極の底面に対向する前記半導体基板との間に、前記容量絶縁膜を介して前記第2容量電極の第1部分が設けられている、半導体装置。 - 請求項7記載の半導体装置において、
前記第1容量電極を挟んで隣接する前記第2容量電極が、前記第1部分を通じて電気的に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2突出部の突出端部にテーパが形成されている、半導体装置。 - 半導体基板に配置されたメモリ領域と、
前記半導体基板に配置された容量素子領域と、
を備え、
前記メモリ領域のメモリセルは、
前記半導体基板の一部で形成され、前記半導体基板の主面から第1方向に突出し、第2方向に幅を有し、前記第2方向に交差する第3方向に延在し、前記第2方向に沿って配置された複数の第1突出部と、
前記第1突出部との間に第1ゲート絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1ゲート電極と、
前記第1突出部との間に第2ゲート絶縁膜を介して配置され、前記複数の第1ゲート電極の各々の側面に前記第2ゲート絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2ゲート電極と、
前記第2ゲート絶縁膜を介して互いに隣接する前記第1ゲート電極および前記第2ゲート電極を挟むように、前記第1突出部に設けられた第1半導体領域および第2半導体領域と、
を備え、
前記容量素子領域の容量素子は、
前記半導体基板の一部で形成され、前記半導体基板の主面から前記第1方向に突出し、前記第2方向に幅を有し、前記第3方向に延在し、前記第2方向に沿って配置された複数の第2突出部と、
前記第2突出部との間に絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1容量電極と、
前記第2突出部との間に容量絶縁膜を介して配置され、前記複数の第1容量電極の各々の側面に前記容量絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2容量電極と、
を備え、
前記第1ゲート電極と前記第1容量電極とは、第1導体膜で形成され、
前記第2ゲート電極と前記第2容量電極とは、第2導体膜で形成され、
前記複数の第1容量電極の隣接間隔は、前記第1ゲート電極の隣接間隔より小さい、半導体装置。 - 請求項10記載の半導体装置において、
前記複数の第1容量電極の隣接間隔は、前記容量絶縁膜の厚さの3倍以上である、半導体装置。 - 請求項10記載の半導体装置において、
前記第1容量電極の前記第3方向の幅が、前記第1ゲート電極の前記第3方向の幅より小さい、半導体装置。 - 請求項10記載の半導体装置において、
前記複数の第2突出部の隣接間に配置された前記第2容量電極の前記第1方向の長さが、前記複数の第1突出部の隣接間に配置された前記第2ゲート電極の前記第1方向の長さより長い、半導体装置。 - 請求項13記載の半導体装置において、
前記複数の第2突出部の隣接間に配置された前記第1容量電極と、前記第1容量電極の底面に対向する前記半導体基板との間に、前記容量絶縁膜を介して前記第2容量電極の第1部分が設けられている、半導体装置。 - 請求項14記載の半導体装置において、
前記第1容量電極を挟んで隣接する前記第2容量電極が、前記第1部分を通じて電気的に接続されている、半導体装置。 - 請求項10記載の半導体装置において、
前記第2突出部の突出端部にテーパが形成されている、半導体装置。 - 半導体基板に配置されたメモリ領域と、
前記半導体基板に配置された容量素子領域と、
を備え、
前記メモリ領域のメモリセルは、
前記半導体基板の一部で形成され、前記半導体基板の主面から第1方向に突出し、第2方向に幅を有し、前記第2方向に交差する第3方向に延在し、前記第2方向に沿って配置された複数の第1突出部と、
前記第1突出部との間に第1ゲート絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1ゲート電極と、
前記第1突出部との間に第2ゲート絶縁膜を介して配置され、前記複数の第1ゲート電極の各々の側面に前記第2ゲート絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2ゲート電極と、
前記第2ゲート絶縁膜を介して互いに隣接する前記第1ゲート電極および前記第2ゲート電極を挟むように、前記第1突出部に設けられた第1半導体領域および第2半導体領域と、
を備え、
前記容量素子領域の容量素子は、
前記半導体基板の一部で形成され、前記半導体基板の主面から前記第1方向に突出し、前記第2方向に幅を有し、前記第3方向に延在し、前記第2方向に沿って配置された複数の第2突出部と、
前記第2突出部との間に絶縁膜を介して配置され、前記第2方向に延在し、前記第3方向に沿って配置された複数の第1容量電極と、
前記第2突出部との間に容量絶縁膜を介して配置され、前記複数の第1容量電極の各々の側面に前記容量絶縁膜を介して隣接し、前記第2方向に延在し、前記第3方向に沿って配置された複数の第2容量電極と、
を備え、
前記第1ゲート電極と前記第1容量電極とは、第1導体膜で形成され、
前記第2ゲート電極と前記第2容量電極とは、第2導体膜で形成され、
前記複数の第2突出部の隣接間に配置された前記第2容量電極の前記第1方向の長さが、前記複数の第1突出部の隣接間に配置された前記第2ゲート電極の前記第1方向の長さより長い、半導体装置。 - 請求項17記載の半導体装置において、
前記複数の第2突出部の隣接間に配置された前記第1容量電極と、前記第1容量電極の底面に対向する前記半導体基板との間に、前記容量絶縁膜を介して前記第2容量電極の第1部分が設けられている、半導体装置。 - 請求項18記載の半導体装置において、
前記第1容量電極を挟んで隣接する前記第2容量電極が、前記第1部分を通じて電気的に接続されている、半導体装置。 - 請求項17記載の半導体装置において、
前記第1容量電極の前記第3方向の幅が、前記第1ゲート電極の前記第3方向の幅より小さい、半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017090251A JP6885779B2 (ja) | 2017-04-28 | 2017-04-28 | 半導体装置 |
US15/904,349 US10249638B2 (en) | 2017-04-28 | 2018-02-24 | Semiconductor device |
EP18159547.1A EP3396701A1 (en) | 2017-04-28 | 2018-03-01 | Semiconductor device |
TW107113278A TWI752220B (zh) | 2017-04-28 | 2018-04-19 | 半導體裝置 |
CN201810367957.8A CN108807415B (zh) | 2017-04-28 | 2018-04-23 | 半导体设备 |
KR1020180047102A KR20180121376A (ko) | 2017-04-28 | 2018-04-24 | 반도체 장치 |
US16/269,797 US10559581B2 (en) | 2017-04-28 | 2019-02-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017090251A JP6885779B2 (ja) | 2017-04-28 | 2017-04-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018190788A true JP2018190788A (ja) | 2018-11-29 |
JP6885779B2 JP6885779B2 (ja) | 2021-06-16 |
Family
ID=61563170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017090251A Active JP6885779B2 (ja) | 2017-04-28 | 2017-04-28 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (2) | US10249638B2 (ja) |
EP (1) | EP3396701A1 (ja) |
JP (1) | JP6885779B2 (ja) |
KR (1) | KR20180121376A (ja) |
CN (1) | CN108807415B (ja) |
TW (1) | TWI752220B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6885779B2 (ja) * | 2017-04-28 | 2021-06-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10497794B1 (en) * | 2018-10-09 | 2019-12-03 | Nxp Usa, Inc. | Fin field-effect transistor (FinFet) capacitor structure for use in integrated circuits |
JP2020155485A (ja) * | 2019-03-18 | 2020-09-24 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP7262322B2 (ja) * | 2019-06-20 | 2023-04-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN112530933B (zh) * | 2019-09-18 | 2024-03-22 | 铠侠股份有限公司 | 半导体装置 |
JP2022143282A (ja) * | 2021-03-17 | 2022-10-03 | キオクシア株式会社 | 半導体装置及びその製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080057644A1 (en) * | 2006-08-31 | 2008-03-06 | Dong-Hwa Kwak | Semiconductor devices having a convex active region and methods of forming the same |
US20130270620A1 (en) * | 2012-04-11 | 2013-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for finfet integrated with capacitor |
JP2014078661A (ja) * | 2012-10-12 | 2014-05-01 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2014229844A (ja) * | 2013-05-27 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20160190143A1 (en) * | 2014-12-24 | 2016-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitor to integrate with flash memory |
JP2017045860A (ja) * | 2015-08-26 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017063188A (ja) * | 2015-09-25 | 2017-03-30 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | スプリットゲートフラッシュ技術におけるインターディジテートキャパシタ |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010183022A (ja) * | 2009-02-09 | 2010-08-19 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US9293584B2 (en) | 2011-11-02 | 2016-03-22 | Broadcom Corporation | FinFET devices |
JP5936959B2 (ja) | 2012-09-04 | 2016-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9520404B2 (en) * | 2013-07-30 | 2016-12-13 | Synopsys, Inc. | Asymmetric dense floating gate nonvolatile memory with decoupled capacitor |
KR102132845B1 (ko) * | 2014-02-11 | 2020-07-13 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 |
JP6466211B2 (ja) * | 2015-03-11 | 2019-02-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2017037986A (ja) * | 2015-08-11 | 2017-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9673207B2 (en) * | 2015-08-20 | 2017-06-06 | Sandisk Technologies Llc | Shallow trench isolation trenches and methods for NAND memory |
JP6885779B2 (ja) * | 2017-04-28 | 2021-06-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2017
- 2017-04-28 JP JP2017090251A patent/JP6885779B2/ja active Active
-
2018
- 2018-02-24 US US15/904,349 patent/US10249638B2/en active Active
- 2018-03-01 EP EP18159547.1A patent/EP3396701A1/en not_active Withdrawn
- 2018-04-19 TW TW107113278A patent/TWI752220B/zh active
- 2018-04-23 CN CN201810367957.8A patent/CN108807415B/zh active Active
- 2018-04-24 KR KR1020180047102A patent/KR20180121376A/ko active IP Right Grant
-
2019
- 2019-02-07 US US16/269,797 patent/US10559581B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080057644A1 (en) * | 2006-08-31 | 2008-03-06 | Dong-Hwa Kwak | Semiconductor devices having a convex active region and methods of forming the same |
US20130270620A1 (en) * | 2012-04-11 | 2013-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for finfet integrated with capacitor |
JP2014078661A (ja) * | 2012-10-12 | 2014-05-01 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2014229844A (ja) * | 2013-05-27 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20160190143A1 (en) * | 2014-12-24 | 2016-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitor to integrate with flash memory |
JP2017045860A (ja) * | 2015-08-26 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017063188A (ja) * | 2015-09-25 | 2017-03-30 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | スプリットゲートフラッシュ技術におけるインターディジテートキャパシタ |
Also Published As
Publication number | Publication date |
---|---|
JP6885779B2 (ja) | 2021-06-16 |
US20190172837A1 (en) | 2019-06-06 |
EP3396701A1 (en) | 2018-10-31 |
US10559581B2 (en) | 2020-02-11 |
TW201903974A (zh) | 2019-01-16 |
CN108807415A (zh) | 2018-11-13 |
US10249638B2 (en) | 2019-04-02 |
KR20180121376A (ko) | 2018-11-07 |
TWI752220B (zh) | 2022-01-11 |
US20180315768A1 (en) | 2018-11-01 |
CN108807415B (zh) | 2023-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106486489B (zh) | 半导体装置 | |
TWI752220B (zh) | 半導體裝置 | |
CN106558588B (zh) | 半导体装置 | |
TWI517413B (zh) | 非揮發性記憶體結構 | |
JP4901325B2 (ja) | 半導体装置 | |
US9543315B1 (en) | Semiconductor device | |
JP6235901B2 (ja) | 半導体装置 | |
JP3947135B2 (ja) | 不揮発性半導体記憶装置 | |
JP2007294595A (ja) | 不揮発性半導体メモリ | |
KR20170099769A (ko) | 반도체 장치의 제조 방법 | |
JP2013197536A (ja) | 半導体記憶装置 | |
JP6026919B2 (ja) | 半導体装置の製造方法 | |
JP7038607B2 (ja) | 半導体装置およびその製造方法 | |
JP2008218625A (ja) | 半導体装置およびその製造方法 | |
JP2019050255A (ja) | 半導体装置およびその製造方法 | |
US20160260795A1 (en) | Method of manufacturing semiconductor device | |
JP2016051822A (ja) | 半導体装置の製造方法 | |
JP2011035169A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
US11205655B2 (en) | Method for manufacturing semiconductor device including fin-structured transistor | |
KR100660718B1 (ko) | 플래시 메모리 소자의 플로팅 게이트 어레이 형성 방법 | |
KR20130039795A (ko) | 낸드 플래시 메모리 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191018 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200917 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200929 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201110 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20210427 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210513 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6885779 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |