JP2018173782A5 - - Google Patents

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Publication number
JP2018173782A5
JP2018173782A5 JP2017071079A JP2017071079A JP2018173782A5 JP 2018173782 A5 JP2018173782 A5 JP 2018173782A5 JP 2017071079 A JP2017071079 A JP 2017071079A JP 2017071079 A JP2017071079 A JP 2017071079A JP 2018173782 A5 JP2018173782 A5 JP 2018173782A5
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JP
Japan
Prior art keywords
delay amount
delay
storage unit
write
control circuit
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JP2017071079A
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English (en)
Japanese (ja)
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JP2018173782A (ja
JP6832777B2 (ja
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Priority claimed from JP2017071079A external-priority patent/JP6832777B2/ja
Priority to JP2017071079A priority Critical patent/JP6832777B2/ja
Priority to US15/889,928 priority patent/US10504570B2/en
Priority to TW107108941A priority patent/TWI765987B/zh
Priority to EP18165131.6A priority patent/EP3382713B1/en
Priority to CN201810288453.7A priority patent/CN108694974B/zh
Publication of JP2018173782A publication Critical patent/JP2018173782A/ja
Publication of JP2018173782A5 publication Critical patent/JP2018173782A5/ja
Publication of JP6832777B2 publication Critical patent/JP6832777B2/ja
Application granted granted Critical
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JP2017071079A 2017-03-31 2017-03-31 半導体装置 Active JP6832777B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2017071079A JP6832777B2 (ja) 2017-03-31 2017-03-31 半導体装置
US15/889,928 US10504570B2 (en) 2017-03-31 2018-02-06 Semiconductor device and timing calibration method
TW107108941A TWI765987B (zh) 2017-03-31 2018-03-16 半導體裝置
EP18165131.6A EP3382713B1 (en) 2017-03-31 2018-03-29 Semiconductor device and timing calibration method
CN201810288453.7A CN108694974B (zh) 2017-03-31 2018-03-30 半导体装置和时序校准方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017071079A JP6832777B2 (ja) 2017-03-31 2017-03-31 半導体装置

Publications (3)

Publication Number Publication Date
JP2018173782A JP2018173782A (ja) 2018-11-08
JP2018173782A5 true JP2018173782A5 (https=) 2019-11-21
JP6832777B2 JP6832777B2 (ja) 2021-02-24

Family

ID=61952534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017071079A Active JP6832777B2 (ja) 2017-03-31 2017-03-31 半導体装置

Country Status (5)

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US (1) US10504570B2 (https=)
EP (1) EP3382713B1 (https=)
JP (1) JP6832777B2 (https=)
CN (1) CN108694974B (https=)
TW (1) TWI765987B (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923166B2 (en) 2018-02-27 2021-02-16 SK Hynix Inc. Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices
US11232820B2 (en) * 2018-02-27 2022-01-25 SK Hynix Inc. Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices
KR102679157B1 (ko) * 2018-10-30 2024-06-27 삼성전자주식회사 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
KR102693546B1 (ko) * 2018-11-07 2024-08-08 삼성전자주식회사 스토리지 장치
KR102691395B1 (ko) * 2018-12-20 2024-08-05 에스케이하이닉스 주식회사 메모리 시스템, 메모리 시스템의 동작 방법 및 메모리 콘트롤러
JP7081477B2 (ja) * 2018-12-26 2022-06-07 コニカミノルタ株式会社 画像処理装置、画像処理装置の制御方法、およびプログラム
JP7332406B2 (ja) * 2019-09-13 2023-08-23 キオクシア株式会社 メモリシステム
KR102771802B1 (ko) * 2019-09-26 2025-02-20 삼성전자주식회사 스토리지 장치
CN111009271B (zh) * 2019-11-18 2020-09-29 广东高云半导体科技股份有限公司 基于fpga的psram存储器初始化方法、装置、设备及介质
JP2021149659A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体集積回路、メモリコントローラ、およびメモリシステム
KR102866520B1 (ko) 2020-05-06 2025-10-01 삼성전자주식회사 저장 장치 및 그것의 리트레이닝 방법
KR102815323B1 (ko) * 2020-06-23 2025-06-02 에스케이하이닉스 주식회사 반도체 장치 및 이의 동작 방법
US11726721B2 (en) 2020-09-09 2023-08-15 Samsung Electronics Co., Ltd. Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system
US11677537B2 (en) * 2021-03-17 2023-06-13 Micron Technology, Inc. Signal delay control and related apparatuses, systems, and methods
KR20230165586A (ko) 2022-05-27 2023-12-05 삼성전자주식회사 데이터 입출력 전압을 찾는 메모리 컨트롤러, 메모리 시스템 및 그것의 동작 방법
CN115344215B (zh) * 2022-08-29 2025-03-18 深圳市紫光同创电子股份有限公司 存储器训练方法及系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009082502A1 (en) * 2007-12-21 2009-07-02 Rambus Inc. Method and apparatus for calibrating write timing in a memory system
JP5268392B2 (ja) * 2008-03-07 2013-08-21 パナソニック株式会社 メモリデバイス及びメモリシステム並びにメモリシステムにおけるアクセスタイミング調整方法
JPWO2010137330A1 (ja) * 2009-05-27 2012-11-12 パナソニック株式会社 遅延調整装置、遅延調整方法
JP2011003088A (ja) * 2009-06-19 2011-01-06 Panasonic Corp データラッチ調整装置およびそれを用いたメモリアクセスシステム
JP5653177B2 (ja) * 2010-11-04 2015-01-14 ルネサスエレクトロニクス株式会社 メモリインターフェース回路及び半導体装置
JP6179206B2 (ja) * 2013-06-11 2017-08-16 株式会社リコー メモリ制御装置
US9524799B2 (en) * 2014-12-30 2016-12-20 Sandisk Technologies Llc Method and apparatus to tune a toggle mode interface

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