TWI765987B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI765987B
TWI765987B TW107108941A TW107108941A TWI765987B TW I765987 B TWI765987 B TW I765987B TW 107108941 A TW107108941 A TW 107108941A TW 107108941 A TW107108941 A TW 107108941A TW I765987 B TWI765987 B TW I765987B
Authority
TW
Taiwan
Prior art keywords
delay amount
delay
adjustment
data
write data
Prior art date
Application number
TW107108941A
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English (en)
Chinese (zh)
Other versions
TW201843678A (zh
Inventor
螢原孝征
Original Assignee
日商瑞薩電子股份有限公司
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Publication date
Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201843678A publication Critical patent/TW201843678A/zh
Application granted granted Critical
Publication of TWI765987B publication Critical patent/TWI765987B/zh

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Pulse Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
TW107108941A 2017-03-31 2018-03-16 半導體裝置 TWI765987B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017071079A JP6832777B2 (ja) 2017-03-31 2017-03-31 半導体装置
JP2017-071079 2017-03-31

Publications (2)

Publication Number Publication Date
TW201843678A TW201843678A (zh) 2018-12-16
TWI765987B true TWI765987B (zh) 2022-06-01

Family

ID=61952534

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107108941A TWI765987B (zh) 2017-03-31 2018-03-16 半導體裝置

Country Status (5)

Country Link
US (1) US10504570B2 (https=)
EP (1) EP3382713B1 (https=)
JP (1) JP6832777B2 (https=)
CN (1) CN108694974B (https=)
TW (1) TWI765987B (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923166B2 (en) 2018-02-27 2021-02-16 SK Hynix Inc. Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices
US11232820B2 (en) * 2018-02-27 2022-01-25 SK Hynix Inc. Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices
KR102679157B1 (ko) * 2018-10-30 2024-06-27 삼성전자주식회사 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
KR102693546B1 (ko) * 2018-11-07 2024-08-08 삼성전자주식회사 스토리지 장치
KR102691395B1 (ko) * 2018-12-20 2024-08-05 에스케이하이닉스 주식회사 메모리 시스템, 메모리 시스템의 동작 방법 및 메모리 콘트롤러
JP7081477B2 (ja) * 2018-12-26 2022-06-07 コニカミノルタ株式会社 画像処理装置、画像処理装置の制御方法、およびプログラム
JP7332406B2 (ja) * 2019-09-13 2023-08-23 キオクシア株式会社 メモリシステム
KR102771802B1 (ko) * 2019-09-26 2025-02-20 삼성전자주식회사 스토리지 장치
CN111009271B (zh) * 2019-11-18 2020-09-29 广东高云半导体科技股份有限公司 基于fpga的psram存储器初始化方法、装置、设备及介质
JP2021149659A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体集積回路、メモリコントローラ、およびメモリシステム
KR102866520B1 (ko) 2020-05-06 2025-10-01 삼성전자주식회사 저장 장치 및 그것의 리트레이닝 방법
KR102815323B1 (ko) * 2020-06-23 2025-06-02 에스케이하이닉스 주식회사 반도체 장치 및 이의 동작 방법
US11726721B2 (en) 2020-09-09 2023-08-15 Samsung Electronics Co., Ltd. Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system
US11677537B2 (en) * 2021-03-17 2023-06-13 Micron Technology, Inc. Signal delay control and related apparatuses, systems, and methods
KR20230165586A (ko) 2022-05-27 2023-12-05 삼성전자주식회사 데이터 입출력 전압을 찾는 메모리 컨트롤러, 메모리 시스템 및 그것의 동작 방법
CN115344215B (zh) * 2022-08-29 2025-03-18 深圳市紫光同创电子股份有限公司 存储器训练方法及系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090161453A1 (en) * 2007-12-21 2009-06-25 Rambus Inc. Method and apparatus for calibrating write timing in a memory system
US20100146237A1 (en) * 2008-03-07 2010-06-10 Yuji Takai Memory device, memory system, and access timing adjusting method in memory system
US20120113729A1 (en) * 2010-11-04 2012-05-10 Renesas Electronics Corporation Memory interface circuit and semiconductor device
US20160189758A1 (en) * 2014-12-30 2016-06-30 Sandisk Technologies Inc. Method and apparatus to tune a toggle mode interface

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010137330A1 (ja) * 2009-05-27 2012-11-12 パナソニック株式会社 遅延調整装置、遅延調整方法
JP2011003088A (ja) * 2009-06-19 2011-01-06 Panasonic Corp データラッチ調整装置およびそれを用いたメモリアクセスシステム
JP6179206B2 (ja) * 2013-06-11 2017-08-16 株式会社リコー メモリ制御装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090161453A1 (en) * 2007-12-21 2009-06-25 Rambus Inc. Method and apparatus for calibrating write timing in a memory system
US20100146237A1 (en) * 2008-03-07 2010-06-10 Yuji Takai Memory device, memory system, and access timing adjusting method in memory system
US20120113729A1 (en) * 2010-11-04 2012-05-10 Renesas Electronics Corporation Memory interface circuit and semiconductor device
US20160189758A1 (en) * 2014-12-30 2016-06-30 Sandisk Technologies Inc. Method and apparatus to tune a toggle mode interface

Also Published As

Publication number Publication date
TW201843678A (zh) 2018-12-16
US20180286471A1 (en) 2018-10-04
JP2018173782A (ja) 2018-11-08
CN108694974A (zh) 2018-10-23
EP3382713A1 (en) 2018-10-03
CN108694974B (zh) 2023-11-10
EP3382713B1 (en) 2023-07-19
US10504570B2 (en) 2019-12-10
JP6832777B2 (ja) 2021-02-24

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