JP2018157200A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 194
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 37
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 13
- 238000004088 simulation Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000000605 extraction Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2005−175425号公報
[特許文献2] 特開2007−324539号公報
ウェル領域は、半導体基板の表面から第1のトレンチ部よりも深い位置にまで設けられ、かつ、第1のトレンチ部の外側から内側に延伸して第1開口の直下の位置まで設けられてよい。
エミッタ領域は、第1のトレンチ部と第1のトレンチ部に隣接して設けられる第2のトレンチ部との間に設けられてよい。
Claims (11)
- 半導体基板と、
前記半導体基板上に設けられた層間絶縁膜と、
前記層間絶縁膜上に設けられたエミッタ電極とを備える半導体装置において、
前記半導体基板は、
前記半導体基板の表面から予め定められた深さまで設けられ、前記半導体基板を上面視した場合に長手部分と短手部分とを含む第1のトレンチ部と、
少なくとも一部が前記表面に露出し、前記第1のトレンチ部によって囲まれた、第1導電型のフローティング半導体領域と
を有し、
前記層間絶縁膜は、前記エミッタ電極と前記フローティング半導体領域とを電気的に接続する複数の開口を有し、
前記複数の開口は、前記長手部分と平行な方向において前記フローティング半導体領域の外側端部に最も近接する第1開口と、前記長手部分と平行な方向において前記外側端部に2番目に近接する第2開口とを含み、
前記第1開口と前記第2開口との距離は、前記複数の開口のうち前記第1開口以外のいずれか二つの隣り合う開口間の距離よりも短い
半導体装置。 - 前記第1開口と前記第2開口との距離は、前記複数の開口のうち前記第1開口以外の二つの隣り合う全ての開口間の距離よりも短い
請求項1に記載の半導体装置。 - 前記第1開口の開口面積は、前記複数の開口のうち前記第1開口以外の各開口の開口面積よりも大きい
請求項1または2に記載の半導体装置。 - 前記半導体基板を上面視した場合に、前記第1開口の外側端部は、前記第1のトレンチ部の前記短手部分に対応して前記短手部分と平行である
請求項1から3のいずれか一項に記載の半導体装置。 - 前記半導体基板を上面視した場合に、前記第1開口の外側端部は、前記第1のトレンチ部の前記長手部分と直交する方向に延伸する
請求項1から4のいずれか一項に記載の半導体装置。 - 前記半導体基板を上面視した場合に、前記複数の開口のうち前記第1開口以外の開口は前記第1のトレンチ部の前記長手部分と平行な方向に長辺を有する
請求項1から5のいずれか一項に記載の半導体装置。 - 前記半導体基板は、
前記表面から前記第1のトレンチ部よりも深い位置にまで設けられ、かつ、前記第1のトレンチ部の外側から内側に延伸して前記第1開口の直下の位置まで設けられる、第1導電型のウェル領域をさらに有する
請求項1から6のいずれか一項に記載の半導体装置。 - 前記半導体基板を上面視した場合に、前記第1開口は、前記第1のトレンチ部と前記第1のトレンチ部に隣接して設けられる第2のトレンチ部との間に設けられる第2導電型のエミッタ領域に比べて、前記第1のトレンチ部の前記長手部分と平行な方向において前記短手部分に近い位置に設けられる
請求項1から7のいずれか一項に記載の半導体装置。 - 前記フローティング半導体領域は、
前記複数の開口が設けられる位置に対応して前記表面に露出して設けられた、第1導電型のコンタクト領域を有する
請求項1から8のいずれか一項に記載の半導体装置。 - 前記半導体基板は、
前記半導体基板の裏面に露出する第1導電型のコレクタ領域と、
前記コレクタ領域上に設けられる第2導電型のフィールドストップ層と、
前記フィールドストップ層上に設けられ、前記第1のトレンチ部の底部と接触する第2導電型のドリフト領域と
をさらに有し、
前記フィールドストップ層は、深さ方向において1つ以上のドーピング濃度のピークを有し、
前記1つ以上のドーピング濃度のピークのうち前記表面に最も近いピークは、前記裏面から5μm以上離れている
請求項1から9のいずれか一項に記載の半導体装置。 - 前記第2開口と前記長手部分と平行な方向において前記第2開口に最も近接する第3開口との距離は、50μm以上100μm以下である
請求項1から10のいずれか一項に記載の半導体装置。
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WO2022249753A1 (ja) * | 2021-05-24 | 2022-12-01 | 富士電機株式会社 | 半導体装置 |
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JP6626929B1 (ja) * | 2018-06-29 | 2019-12-25 | 京セラ株式会社 | 半導体デバイス及び電気装置 |
KR20210097481A (ko) | 2020-01-30 | 2021-08-09 | 주식회사 엘지에너지솔루션 | 공통 모드 전압 모니터링 장치 및 모니터링 방법 |
CN116884996A (zh) * | 2023-09-08 | 2023-10-13 | 深圳芯能半导体技术有限公司 | 一种降低关断损耗的igbt芯片及其制作方法 |
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WO2016098409A1 (ja) * | 2014-12-19 | 2016-06-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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US3704398A (en) * | 1970-02-14 | 1972-11-28 | Nippon Electric Co | Multi-emitter power transistor having emitter region arrangement for achieving substantially uniform emitter-base junction temperatures |
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WO2022249753A1 (ja) * | 2021-05-24 | 2022-12-01 | 富士電機株式会社 | 半導体装置 |
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