CN109075199A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109075199A
CN109075199A CN201780020128.6A CN201780020128A CN109075199A CN 109075199 A CN109075199 A CN 109075199A CN 201780020128 A CN201780020128 A CN 201780020128A CN 109075199 A CN109075199 A CN 109075199A
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illusory
semiconductor device
conductive part
semiconductor substrate
groove
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CN201780020128.6A
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CN109075199B (zh
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内藤达也
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

如果将具有为发射极电位的导电部的虚设沟槽部相对于栅极沟槽部的比率提高，则集电极‑栅极间电容(以下称为CCG)减小，集电极‑发射极间电容(以下称为CCE)增加。由此，容易产生振荡现象。本发明提供一种半导体装置，包括：第一导电型的半导体基板；第二导电型的基区，其设置于半导体基板内的表面侧；栅极沟槽部，其以从半导体基板的表面起贯穿基区的方式设置在半导体基板内，且具有栅极导电部；以及虚设沟槽部，其以从半导体基板的表面起贯穿基区的方式设置在半导体基板内，且包括上部虚设导电部和下部栅极导电部，所述上部虚设导电部具有发射极电位，所述下部栅极导电部位于上部虚设导电部之下且具有栅极电位，虚设沟槽部的下部栅极导电部与栅极沟槽部的栅极导电部连接。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
已知将栅极沟槽设置成矩形环状(例如参照专利文献1)。另外，已知将栅极沟槽和虚设沟槽分别设置成矩形环状(例如参照专利文献2)。
现有技术文献
专利文献
专利文献1：日本特开2013-150000号公报
专利文献2：日本特开2016-092177号公报
发明内容
技术问题
如果将具有为发射极电位的导电部的虚设沟槽部相对于栅极沟槽部的比率提高，则集电极-栅极间电容(以下称为CCG)减小，集电极-发射极间电容(以下称为CCE)增加。由此，容易产生振荡现象。
技术方案
在本发明的第一方式中，提供一种半导体装置。半导体装置可以具备半导体基板、基区、栅极沟槽部和虚设沟槽部。半导体基板可以为第一导电型。基区可以设置于半导体基板内的表面侧。基区可以为第二导电型。栅极沟槽部可以以从半导体基板的表面起贯穿基区的方式设置在半导体基板内。栅极沟槽部可以具有栅极导电部。虚设沟槽部可以以从半导体基板的表面起贯穿基区的方式设置在半导体基板内。虚设沟槽部可以包括上部虚设导电部和下部栅极导电部。上部虚设导电部可以具有发射极电位。下部栅极导电部可以位于上部虚设导电部之下。下部栅极导电部可以具有栅极电位。虚设沟槽部的下部栅极导电部可以与栅极沟槽部的栅极导电部连接。
在半导体基板的表面，多个栅极沟槽部与多个虚设沟槽部可以包围台面区。台面区可以设置于半导体装置的晶体管部。台面区可以具有基区。
在半导体基板的表面，虚设沟槽部可以具有第一直线部、第二直线部和交叉部。第一直线部可以沿着第一方向延伸。第二直线部可以沿着第二方向延伸。第二方向可以与第一方向正交。在交叉部，第一直线部与第二直线部可以相交。
在半导体基板的表面，多个台面区可以在第一方向和第二方向上呈直线状地排列设置。
在半导体基板的表面，设置于半导体装置的晶体管部且分别具有基区的多个台面区可以包括第一组、第二组和第三组。在第一组中，各台面区可以在第一方向上呈直线状地排列设置。在第二组中，各台面区可以在第一方向上呈直线状地排列设置。在第二组中，各台面区可以在第二方向上最接近第一组。在第二组中，各台面区可以以相对于第一组的各台面区在第一方向上相互错开半个周期的方式设置。在第三组中，各台面区可以在第一方向上呈直线状地排列设置。在第三组中，各台面区可以在第二方向上第二接近第一组。在第三组中，各台面区可以相对于第一组的各台面区在第二方向上相互排列地设置。
虚设沟槽部可以在半导体基板的表面以与台面区的平行于第一方向的边邻接的方式设置。栅极沟槽部可以在半导体基板的表面以与台面区的平行于第二方向的边邻接的方式设置。
半导体装置可以还具备与半导体装置的晶体管部邻接的二极管部。设置于晶体管部和二极管部的多个虚设沟槽部可以分别具有下部栅极导电部。
多个虚设沟槽部中的至少一个虚设沟槽部可以不具有下部栅极导电部。
半导体装置可以还具备与半导体装置的晶体管部邻接的二极管部。晶体管部中的多个虚设沟槽部中的最接近二极管部的多个第二直线部中，在第二方向上相邻的第二直线部彼此可以相互连结。最接近二极管部的多个第二直线部可以不具有下部栅极导电部。
虚设沟槽部的下部栅极导电部可以设置于比基区靠近下方的位置。
虚设沟槽部可以具有上部绝缘膜和下部绝缘膜。上部绝缘膜可以设置于上部虚设导电部的侧部和底部。下部绝缘膜可以设置于下部栅极导电部的侧部和底部。下部绝缘膜可以比上部绝缘膜厚。
半导体基板可以具有第一导电型的漂移区。漂移区可以位于比基区靠近下方的位置。虚设沟槽部的上部绝缘膜可以不与漂移区接触。虚设沟槽部的下部绝缘膜可以与漂移区接触。
应予说明，上述的发明内容未列举本发明的所有必要特征。另外，这些特征群的子组合也另外能够成为发明。
附图说明
图1是第一实施方式中的半导体装置100的俯视图。
图2是表示图1的A-A'截面的图。
图3是表示图1的B-B'截面的图。
图4是表示图1的C-C'截面的图。
图5是表示图1的D-D'截面的图。
图6A是表示第一实施方式中的台面区19、虚设沟槽部30和栅极沟槽部40的图。
图6B是表示第一实施方式的变形例中的台面区19、虚设沟槽部30和栅极沟槽部40的图。
图7是表示虚设沟槽部30的变形例的图。
图8是表示第二实施方式中的半导体装置100的D-D'截面的图。
图9是第三实施方式中的半导体装置100的俯视图。
图10是表示第三实施方式中的半导体装置100的D-D'截面的图。
图11是第四实施方式中的半导体装置100的俯视图。
图12是表示第四实施方式中的半导体装置100的F-F'截面的图。
图13是第五实施方式中的半导体装置100的俯视图。
图14是第六实施方式中的半导体装置100的俯视图。
符号说明
10··半导体基板，12··发射区，14··基区，15··接触区，16··蓄积区，18··漂移区，19··台面区，20··缓冲区，22··集电区，24··集电极，26··层间绝缘膜，28··阱区，30··虚设沟槽部，32··上部绝缘膜，33··下部绝缘膜，34··上部虚设导电部，35··下部栅极导电部，36··虚设沟槽，37··第一直线部，38··第二直线部，39··交叉部，40··栅极沟槽部，42··绝缘膜，44··栅极导电部，46··栅极沟槽，50··虚设沟槽部，52··绝缘膜，54··虚设导电部，56··虚设沟槽，62··发射极，64、66、68··接触孔，72··栅极金属层，74··接触孔，80··IGBT部，85··边界部，90··FWD部，92··阴极区，100··半导体装置，119··组
具体实施方式
以下，通过发明的实施方式说明本发明，但以下的实施方式不限定权利要求所涉及的发明。另外，实施方式中说明的特征的所有组合并不限定为发明的解决方案所必须的。
图1是第一实施方式中的半导体装置100的俯视图。本例的半导体装置100具有设置有IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)的IGBT部80和设置有FWD(Free Wheeling Diode：续流二极管)的FWD部90。IGBT部80是晶体管部的一个例子。晶体管部的另一例可以是MOSFET(Metal Oxide Semiconductor Field EffectTransistor：金属氧化物半导体场效应晶体管)。FWD部90是二极管部的一个例子。本例的半导体装置100是将IGBT部80和FWD部90一体地形成于一个半导体基板的RC-IGBT(Reverse-Conducting IGBT：反向导通型IGBT)。
本例的IGBT部80在X方向上与FWD部90邻接。在本例中，X方向与Y方向是彼此正交的方向。X方向是第一方向的一个例子，Y方向是第二方向的一个例子。Z方向是与X-Y平面垂直的方向。X方向、Y方向和Z方向构成所谓的右手系。应予说明，在本例中，“上”和“上方”是指从半导体基板的背面朝向表(正)面的方向(+Z方向)。与此相对，“下”和“下方”是指作为与+Z方向相反方向的-Z方向。在本例中，上和下只是用于说明相对的位置关系的方便的表达。Z方向不一定是指重力方向或与地面垂直的方向。
图1示出半导体基板的端部周边的有源区，省略半导体基板的中心部和位于半导体基板的端部的边缘终止部等其他区域。在俯视时，半导体装置100可以具有包围有源部的边缘终止部。在本例中，有源部是指包含IGBT部80和FWD部90的区域。边缘终止部具有缓和半导体基板的表面侧的电场集中的功能。边缘终止部具有例如保护环、场板、降低表面电场或组合了这些中的两种以上的结构。
本例的半导体装置100在半导体基板内的表面侧具备n+型的发射区12、p-型的基区14、p+型的接触区15、p+型的阱区28、虚设沟槽部30、栅极沟槽部40和虚设沟槽部50。应予说明，n或p分别表示电子或空穴为多数载流子。另外，对标记于n或p的右上方的+或-而言，+表示载流子浓度比未记载+的载流子浓度高，-表示载流子浓度比未记载-的载流子浓度低。
本例的半导体基板为第一导电型的硅基板，但是也可以为第一导电型的碳化硅基板或第一导电型的氮化镓基板。在本例中，第一导电型为n型，本例的半导体基板为n-型的硅基板。第二导电型的基区14设置于IGBT部80和FWD部90。在本例中，第二导电型为p型。应予说明，各例中说明的基板、区域和其他的部分导电型可以分别是相反的导电型。
在图1中示出设置于在半导体基板的表面上设置的层间绝缘膜26的接触孔64、66和74以及设置于FWD部90的层间绝缘膜26的接触孔68。接触孔64、66和68用于发射极62与表面的电连接。与此相对，接触孔74用于栅极金属层72与表面的电连接。
[IGBT部80]本例的IGBT部80具有多个台面区19。各台面区19具有基区14。IGBT部80的基区14在台面区19的周边部中在半导体基板的表面露出。在半导体基板的正面，本例的台面区19的四周被2个栅极沟槽部40和2个虚设沟槽部50包围。本例的虚设沟槽部30与台面区19的与X方向平行的边邻接。另外，本例的栅极沟槽部以与台面区19的与Y方向平行的边邻接的方式设置。应予说明，俯视时的台面区19的形状不限于矩形，还可以为五边形以上的多边形。
本例的IGBT部80的台面区19具有多个发射区12。发射区12在台面区19的周边部在半导体基板的表面露出。本例的发射区12设置于台面区19的±X方向端部且是台面区19的Y方向的中点附近。换言之，在本例中，1个台面区19具有2个发射区12。本例的发射区12具有沿着Y方向延伸的带状。
本例的IGBT部80的台面区19具有接触区15。接触区15在台面区19的中央部中在半导体基板的表面露出。接触区15设置于比台面区19小的范围。本例的接触区15具有与台面区19相似的矩形形状。本例的接触区15在接触孔64的开口部露出。应予说明，本例的接触孔64与接触区15同样地具有与台面区19相似的矩形形状。接触孔64在图1中的边界线的内侧具有开口。例如，发射极62和接触区15在接触孔64的内侧相互连接。
虚设沟槽部30和栅极沟槽部40以从半导体基板的表面侧贯穿基区14的方式设置。在本例中，沟槽部贯穿基区14是指通过蚀刻使设置于整个表面侧的基区14在俯视时分离的状况。
本例的虚设沟槽部30至少具有形成于虚设沟槽的内壁的上部绝缘膜32和形成于内壁被上部绝缘膜32覆盖的虚设沟槽的内部的上部虚设导电部34。上部虚设导电部34介由接触孔66与发射极62连接。应予说明，本例的发射极62从阱区28沿着+Y方向延伸，覆盖整个IGBT部80和整个FWD部90。应予说明，阱区28设置于比位于-Y方向端部的基区14更朝向-Y方向的位置。
虚设沟槽部30具有第一直线部37、第二直线部38和交叉部39。在本例中，在与IGBT部80的-Y方向端部的台面区19邻接的虚设沟槽部30中，示出第一直线部37、第二直线部38和交叉部39。然而，IGBT部80的各虚设沟槽部30可以具有同样的第一直线部37、第二直线部38和交叉部39。
以用虚线包围的方式示出1个第一直线部37和1个第二直线部38。另外，用箭头表示1个交叉部39。第一直线部37沿着X方向延伸。与此相对，第二直线部38沿着Y方向延伸。在本例中，多个第一直线部37与1个第二直线部38正交。将第一直线部37与第二直线部38相交的位置称为交叉部39。
虚设沟槽部30的虚设沟槽具有预定的深度。在本例中，由于除了设置栅极沟槽部40以外还设置虚设沟槽部30，所以能够获得空穴蓄积于沟槽间的载流子蓄积效果。由此，能够降低导通电压。另外，本例的虚设沟槽部30由于不使第一直线部37与第二直线部38分开而在交叉部39正交，所以与不设置交叉部39的情况相比，能够提高载流子蓄积效果。
应予说明，交叉部39的虚设沟槽可以比第一直线部37和第二直线部38的虚设沟槽深。假设在将交叉部39设置于栅极沟槽部40的情况下，交叉部39附近的栅极阈值电压会与第一直线部37和第二直线部38的栅极阈值电压不同。换言之，产生栅极阈值电压因栅极沟槽部40的位置不同而变化的问题。对此，在本例中，由于在虚设沟槽部30设置交叉部39而在栅极沟槽部40不设置交叉部39，所以能够避免栅极阈值电压变化的问题。
栅极沟槽部40具有形成于栅极沟槽的内壁的绝缘膜42和形成于内壁被绝缘膜42覆盖的栅极沟槽的内部的栅极导电部44。栅极导电部44具有控制IGBT的沟道的功能。栅极导电部44介由接触孔74与栅极金属层72连接。本例的栅极金属层72至少覆盖位于-Y方向的端部的虚设沟槽部30和栅极沟槽部40的一部分。本例的栅极金属层72主要设置在阱区28上。
如果对形成于栅极沟槽部40的内部的栅极导电部44施加预定的电压，则在形成于发射区12的下方的p型的基区中与栅极沟槽部40接触的区域形成沟道。如果在对发射极62施加预定的低电位(例如接地电位)且对设置于半导体基板的背面的集电极施加预定的高电位(例如几十伏～几千伏)的情况下形成沟道，则电流从集电极经由沟道流向发射极62。
在本例中，由于利用虚设沟槽部30和栅极沟槽部40包围台面区19，所以在半导体装置100的设计阶段能够容易地调整半导体基板的表面的栅极沟槽部40的密度。具体而言，通过使2个第一直线部37连结，从而能够使栅极沟槽部40为虚设沟槽部30。由此，能够容易地调整栅极沟槽部40的占有面积相对于虚设沟槽部30的占有面积的比率。应予说明，本例的虚设沟槽部30和栅极沟槽部40所具有的沟槽为相同的深度。
应予说明，在本例中，部分位于栅极金属层72下的栅极沟槽部40是沿着Y方向延伸的直线形状。然而，2个该栅极沟槽部40可以在-Y方向端部呈U字状连结。换言之，部分位于栅极金属层72下的2个栅极沟槽部40可以构成U字的长边部而通过U字的短边部相互连结。
另外，还能够通过使栅极沟槽部40的占有面积的比率相对地增加，从而使寄生栅极电容增加，并通过使虚设沟槽部30的占有面积的比率相对地增加，从而降低寄生栅极电容。这样，在本例的半导体装置100中，能够在半导体装置100的设计阶段将寄生栅极电容容易地调整为所希望的值。
[FWD部90]在本例中，在IGBT部80与FWD部90的边界部85附近的FWD部90不具有四周被任意沟槽部包围的台面区19。在边界部85附近的FWD部90中，基区14沿着+Y方向延伸。本例的FWD部90具有虚设沟槽部50。虚设沟槽部50在+X方向与IGBT部80与FWD部90的边界部85附近的基区14邻接。
虚设沟槽部50至少具有形成于虚设沟槽的内壁的绝缘膜52和形成于内壁被绝缘膜52覆盖的虚设沟槽的内部的虚设导电部54。虚设导电部54介由接触孔68与发射极62连接。在被虚设沟槽部50包围的区域设置有多个台面区19。FWD部90中的各台面区19具有基区14。基区14的构成与IGBT部80的基区14相同，因此省略重复的说明。应予说明，FWD部90的台面区19不具有发射区12和接触区15。
图2是表示图1的A-A'截面的图。A-A'截面是穿过IGBT部80和FWD部90的截面图。圆圈包围的“E”、“G”和“C”分别表示发射极端子、栅极端子和集电极端子。发射极端子与位于半导体基板10的表面上的发射极62电连接。与此相对，集电极端子与位于半导体基板10的背面下的集电极24电连接。应予说明，栅极导电部44与发射极62通过层间绝缘膜26相互电分离。
本例的半导体基板10在比基区14靠近背面侧且比栅极沟槽46的底部靠近表面侧的位置具有n+型的蓄积区16。本例的蓄积区16被设置在IGBT部80和FWD部90。半导体基板10在蓄积区16之下具有n-型的漂移区18。换言之，漂移区18位于比基区14靠近下方的位置。另外，半导体基板10在漂移区18之下具有n型的缓冲区20。此外，半导体基板10在IGBT部80中的缓冲区20之下具有p+型的集电区22，在FWD部90中的缓冲区20之下具有n+型的阴极区92。另外，在集电区22和阴极区92之下设置有集电极24。本例的IGBT部80在有源区中位于将集电区22沿与半导体基板10的背面垂直的方向相对于正面投影时的投影区域，且是规则地配置有包含发射区12和接触区15的预定的单位结构的区域。另外，本例的FWD部90在有源区中位于与阴极区92一致的背面的区域，或者将阴极区92沿与半导体基板10的背面垂直的方向相对于正面投影时的投影区域。
缓冲区20的n型杂质浓度比漂移区18的n型杂质浓度高。缓冲区20可以作为防止从基区14的背面侧扩展的耗尽层到达集电区22的场截止层发挥功能。应予说明，在图2中，示出栅极沟槽部40中的栅极沟槽46和虚设沟槽部50中的虚设沟槽56。栅极沟槽46和虚设沟槽56是指通过蚀刻形成的沟槽部的外形。栅极沟槽46和虚设沟槽56可以是相同的深度，也可以是不同的深度。
图3是表示图1的B-B'截面的图。B-B'截面是穿过IGBT部80的虚设沟槽部30和栅极沟槽部40的截面图。圆圈包围的“G”表示栅极端子。栅极端子与栅极金属层72电连接。
虚设沟槽部30具有上部绝缘膜32和上部虚设导电部34以及下部绝缘膜33和下部栅极导电部35。下部栅极导电部35位于上部虚设导电部34之下。下部栅极导电部35设置于内壁被下部绝缘膜33覆盖的虚设沟槽的内部。上部虚设导电部34与下部栅极导电部35通过上部绝缘膜32电分离。
下部栅极导电部35与栅极沟槽部40的栅极导电部44连接。因此，下部栅极导电部35具有栅极电位。与此相对，上部虚设导电部34具有发射极电位。在本例中，栅极导电部44彼此不介由另外的布线和接触孔连接，而是介由下部栅极导电部35将栅极导电部44彼此连接，因此半导体装置100的微细化变得容易。
假设在虚设沟槽部30的导电部全部为发射极电位的导电部的情况下，如果将虚设沟槽部30相对于栅极沟槽部40的占有面积的比率提高，则对应地CCG减小而CCE增加，所以容易产生振荡现象(半导体装置的输出随着栅极的导通关断而振荡的现象)。假设CCG减小，则栅极的开关速度变快。由此，每单位时间的电压变化(dv/dt)变高，因此产生振荡现象。对此，本例中的IGBT部80的虚设沟槽部30具有上部虚设导电部34和下部栅极导电部35的分体结构。由于虚设沟槽部30具有下部栅极导电部35，所以介由下部栅极导电部35形成CCG。在本例中，由于这样设置CCG，所以与虚设沟槽部30不具有栅极电位的导电部的情况相比，即使提高虚设沟槽部30相对于栅极沟槽部40的占有面积的比率，也能够抑制产生振荡现象的情况。
图4是表示图1的C-C'截面的图。C-C'截面是穿过IGBT部80的虚设沟槽部30的截面图。下部栅极导电部35可以设置于比基区14靠近下方的位置。本例的下部栅极导电部35设置于蓄积区16之下。与此相伴，包覆下部栅极导电部35的下部绝缘膜33的底部和侧部与漂移区18接触。与此相对，上部绝缘膜32不与漂移区18接触。
上部虚设导电部34的最下端可以位于蓄积区16的上端和下端之间。上部虚设导电部34的电位与发射极62相同。另外，漂移区18中的n型杂质的掺杂浓度例如为1×1014/cm3左右或其以下。在IGBT进行导通时，因电荷载流子(电子、空穴)的影响而导致漂移区18的电位变化。如果电位与发射极相同的上部虚设导电部34的最下端到达漂移区18，则在与漂移区18接触的沟槽部的侧壁容易形成空穴的反转层。空穴通过该空穴的反转层而进入基区14，电导率调制变得困难。因此，导通时间变长。另一方面，由于蓄积区16的掺杂浓度比漂移区18的掺杂浓度高，所以形成空穴的反转层的电压阈值比漂移区18高。因此，如果上部虚设导电部34的最下端位于蓄积区16的上端与下端之间，则几乎不形成空穴的反转层，能够缩短导通时间。
对图4所示的下部栅极导电部35的制造方法的一个例子进行说明。首先，在半导体基板10的表面形成沿着排列方向延伸的虚设沟槽36和栅极沟槽46。接下来，形成覆盖虚设沟槽36和栅极沟槽46的内壁的绝缘膜。该绝缘膜可以是二氧化硅。接下来，在虚设沟槽部30和栅极沟槽部40内形成多晶硅。由此，形成栅极沟槽部40中的绝缘膜42和栅极导电部44。
接下来，用掩模材料覆盖栅极沟槽部40等，仅使虚设沟槽部30从掩模材料露出。然后，通过蚀刻来局部去除虚设沟槽部30内的绝缘膜和多晶硅。在蚀刻后，残留在虚设沟槽部30内的多晶硅成为下部栅极导电部35，残留在虚设沟槽36的内壁的绝缘膜成为下部绝缘膜33。
接下来，在下部栅极导电部35上形成绝缘膜。该绝缘膜也可以是二氧化硅。由此形成上部绝缘膜32。接下来，与虚设沟槽部30内的上部绝缘膜32接触地形成多晶硅。接下来，保留成为上部虚设导电部34的部分，去除多晶硅。由此，能够形成图4的Y-Z截面所示的结构。
图5是表示图1的D-D'截面的图。D-D'截面是穿过IGBT部80的虚设沟槽部30和FWD部90的虚设沟槽部50的截面图。在本例中，IGBT部80中的虚设沟槽部30的导电部具有上部虚设导电部34和下部栅极导电部35。与此相对，FWD部90的虚设沟槽部50的导电部仅具有虚设导电部54。
作为第一实施方式的第一变形例，虚设沟槽部50可以具有上部虚设导电部34和下部栅极导电部35。换言之，IGBT部80和FWD部90中的虚设沟槽部30和50分别可以具有上部虚设导电部34和下部栅极导电部35。由此，能够消除半导体基板10的表面侧的电位分布的不均衡。
图6A是表示第一实施方式中的台面区19、虚设沟槽部30和栅极沟槽部40的图。在图6A中，为了便于说明，仅示出IGBT部80的台面区19、虚设沟槽部30和栅极沟槽部40，省略其他结构。应予说明，用虚线表示虚设沟槽部30与栅极沟槽部40的边界。
在本例中，多个台面区19被设置成所谓的格子状。换言之，多个台面区19在第一方向和第二方向上呈直线状地排列设置。换言之，在X方向上排列的各台面区19的Y方向位置一致。另外，在Y方向上排列的各台面区19的X方向位置一致。这样，通过虚设沟槽部30和栅极沟槽部40包围各台面区19，能够获得载流子蓄积效果。
图6B是表示第一实施方式的第二变形例中的台面区19、虚设沟槽部30和栅极沟槽部40的图。应予说明，在图6B中，为了便于说明，用实线表示虚设沟槽部30与栅极沟槽部40的边界。在图6B中，也与图6A同样地示出IGBT部80的台面区19、虚设沟槽部30和栅极沟槽部40。
在本例中，多个台面区19被设置成所谓的交错格子状。本例中的多个台面区19包括第一组119-1、在+Y方向上与第一组119-1最接近的第二组119-2和在+Y方向上与第一组119-1第二接近的第三组119-3。
在第一组119-1、第二组119-2和第三组119-3中，各台面区19在X方向上呈直线状地排列设置。第二组119-2的各台面区19以相对于第一组119-1的各台面区19在X方向上相互错开半个周期的方式设置。应予说明，与本例的台面区19相关的1个周期是指在X方向上邻接的台面区19的中心之间的长度。半个周期是指该1个周期的一半的长度。
第三组119-3的各台面区19相对于第一组119-1的各台面区19在Y方向上相互排列。在本例中，第一组119-1和第三组119-3的各台面区19的中心的位置在X方向上一致。可以以在+Y方向与第三组119-3邻接的方式设置与第二组119-2同样的第四组119-4。这样，第一组119-1和第二组119-2的构成可以周期性地在Y方向上重复。应予说明，FWD部90也可以具有与IGBT部80同样的台面区19的配置。在本例中，也能够与图6A的例子同样地获得载流子蓄积效果。
图7是表示虚设沟槽部30的变形例的图。用虚线表示上部绝缘膜32与下部绝缘膜33的边界。然而，在上部绝缘膜32和下部绝缘膜33为相同材料的情况下，观察不到边界也可以。上部绝缘膜32设置于上部虚设导电部34的侧部和底部。下部绝缘膜33除了设置于上部虚设导电部34的底部与下部栅极导电部35的顶部之间以外，还设置于下部栅极导电部35的侧部和底部。本例的下部绝缘膜33的厚度t2比上部绝缘膜32的厚度t1厚。该构成也能够确保抑制振荡现象的CCG。
在本例中，将从表面到上部虚设导电部34的底部的深度记为D1，将从表面到下部栅极导电部35的顶部的深度记为D2。在本例中，深度D2比深度D1深。本例的深度D1比基区14深，且比蓄积区16与漂移区18的边界浅。换言之，本例的上部虚设导电部34的底部位于与蓄积区16相同的深度范围。下部栅极导电部35的顶部可以设置于比深度D1深的位置。
图8是表示第二实施方式中的半导体装置100的D-D'截面的图。多个虚设沟槽部30中的至少一个虚设沟槽部30可以不具有下部栅极导电部35。在本例中，位于-Y方向端部的虚设沟槽部30不具有下部栅极导电部35。位于-Y方向端部的虚设沟槽部30在虚设沟槽36内与虚设沟槽部50同样地具有绝缘膜52和虚设导电部54。在这一方面与第一实施方式不同，但本例也能够获得与第一实施方式同样的有益效果。另外，也可以将本例与第一实施方式的变形例组合。
应予说明，在像本例的虚设沟槽部30和50那样将导电部全部设为虚设导电部54的情况下，可以采用与第一实施例不同的制造方法。例如，通过蚀刻完全去除虚设沟槽部30内的多晶硅。其后，可以通过在整个虚设沟槽部30内形成多晶硅来形成虚设导电部54。
图9是第三实施方式中的半导体装置100的俯视图。在本例中，IGBT部80中的虚设沟槽部30的第一直线部沿着+X方向延伸而与FWD部90中的虚设沟槽部50连结。
图10是表示第三实施方式中的半导体装置100的D-D'截面的图。本例的虚设沟槽部30与第一实施方式同样地具有上部虚设导电部34和下部栅极导电部35。下部栅极导电部35在边界部85终止。但是，上部虚设导电部34与FWD部90中的虚设导电部54连结。在这一方面与第一实施方式不同，但本例也能够获得与第一实施方式同样的有益效果。另外，也可以将本例与第一实施方式的变形例和第二实施方式组合。
图11是第四实施方式中的半导体装置100的俯视图。在本例中，在边界部85配置虚设沟槽部30，不配置栅极沟槽部40。换言之，多个虚设沟槽部30中的最靠近IGBT部80的多个第二直线部38中，在Y方向上相邻的第二直线部38彼此可以相互连结。在本例中，边界部85的虚设沟槽部30不具有下部栅极导电部35。换言之，在本例中，边界部85的虚设沟槽部30与FWD部90的虚设沟槽部50同样地具有绝缘膜52和虚设导电部54。
图12是表示第四实施方式中的半导体装置100的F-F'截面的图。如图12中实线所示，虚设沟槽部30的上部虚设导电部34与边界部85中的虚设沟槽部30的虚设导电部54分开。但是，在其他例中，如虚线所示，上部虚设导电部34可以与虚设导电部54连结。在这一方面与第一实施方式不同，但本例也能够获得与第一实施方式同样的有益效果。另外，也可以将本例与第一实施方式的变形例、第二实施方式和第三实施方式组合。
图13是第五实施方式中的半导体装置100的俯视图。本例的FWD部90的台面区19与IGBT部80的台面区19同样地具有发射区12。在这一方面与第一实施方式不同，但本例也能够获得与第一实施方式同样的有益效果。另外，也可以将本例与第一实施方式的变形例、第二实施方式、第三实施方式和第四实施方式组合。
图14是第六实施方式中的半导体装置100的俯视图。应予说明，在图14中，省略层间绝缘膜26。本例的虚设沟槽部30和50具有所谓的条纹状。本例的虚设沟槽部30和50沿着Y方向平行地设置。虚设沟槽部30不具有第一直线部37，仅具有第二直线部38。因此，虚设沟槽部30不具有交叉部39。在本例中，在多个虚设沟槽部30的各第二直线部38上设置有用于将上部虚设导电部34与发射极62电连接的接触孔66。在这一方面与第一实施方式不同，但本例也能够获得与第一实施方式同样的有益效果。另外，也可以将本例与第一实施方式的变形例组合。也可以将本例与第四实施方式或第五实施方式组合。
以上，利用实施方式说明了本发明，但本发明的技术范围不限于上述实施方式所记载的范围。对于本领域技术人员而言，可以对上述实施方式进行各种变更或改良是明了的。根据权利要求书的记载可知进行了那样的变更或改良的方式也包括在本发明的技术范围内。
应当注意的是，权利要求书、说明书和附图中所示的装置和方法中的工作、顺序、步骤及阶段等各处理的执行顺序只要并未特别明确为“在……之前”，“先于……”等，就可以按任意顺序实现。即使为方便起见，对权利要求书、说明书和附图中的工作流程使用“首先”，“接下来”等进行了说明，也不表示一定要按照该顺序执行。

Claims (12)

1.一种半导体装置，其特征在于，具备：
第一导电型的半导体基板；
第二导电型的基区，其设置于所述半导体基板内的表面侧；
栅极沟槽部，其以从所述半导体基板的表面起贯穿所述基区的方式设置在所述半导体基板内，且具有栅极导电部；以及
虚设沟槽部，其以从所述半导体基板的表面起贯穿所述基区的方式设置在所述半导体基板内，且包括上部虚设导电部和下部栅极导电部，所述上部虚设导电部具有发射极电位，所述下部栅极导电部位于所述上部虚设导电部之下且具有栅极电位，
所述虚设沟槽部的所述下部栅极导电部与所述栅极沟槽部的所述栅极导电部连接。
2.根据权利要求1所述的半导体装置，其特征在于，在所述半导体基板的表面，多个所述栅极沟槽部与多个所述虚设沟槽部包围台面区，所述台面区设置于所述半导体装置的晶体管部，且具有所述基区。
3.根据权利要求2所述的半导体装置，其特征在于，在所述半导体基板的表面，所述虚设沟槽部具有：
第一直线部，其沿着第一方向延伸；
第二直线部，其沿着与所述第一方向正交的第二方向延伸；以及
交叉部，其是所述第一直线部与所述第二直线部相交的部分。
4.根据权利要求3所述的半导体装置，其特征在于，在所述半导体基板的表面，多个所述台面区在第一方向和第二方向上呈直线状地排列设置。
5.根据权利要求3所述的半导体装置，其特征在于，在所述半导体基板的表面，设置于所述半导体装置的晶体管部且分别具有所述基区的多个所述台面区包括：
第一组，第一组的各台面区在所述第一方向上呈直线状地排列设置；
第二组，第二组的各台面区在所述第一方向上呈直线状地排列设置，且在所述第二方向上最接近所述第一组，所述第二组的各台面区以相对于所述第一组的各台面区在所述第一方向上相互错开半个周期的方式设置；以及
第三组，第三组的各台面区在所述第一方向上呈直线状地排列设置，且在所述第二方向上第二接近所述第一组，所述第三组的各台面区相对于所述第一组的各台面区在所述第二方向上相互排列设置。
6.根据权利要求4或5所述的半导体装置，其特征在于，所述虚设沟槽部在所述半导体基板的表面以与所述台面区的平行于所述第一方向的边邻接的方式设置，
所述栅极沟槽部在所述半导体基板的表面以与所述台面区的平行于所述第二方向的边邻接的方式设置。
7.根据权利要求1～6中任一项所述的半导体装置，其特征在于，所述半导体装置还具备与所述半导体装置的晶体管部邻接的二极管部，
设置于所述晶体管部和所述二极管部的多个所述虚设沟槽部分别具备所述下部栅极导电部。
8.根据权利要求3～6中任一项所述的半导体装置，其特征在于，多个所述虚设沟槽部中的至少一个所述虚设沟槽部不具有所述下部栅极导电部。
9.根据权利要求3～6中任一项所述的半导体装置，其特征在于，所述半导体装置还具备与所述半导体装置的晶体管部邻接的二极管部，
所述晶体管部中的多个所述虚设沟槽部中的最接近所述二极管部的多个所述第二直线部中，在所述第二方向上相邻的第二直线部彼此相互连结，且所述最接近所述二极管部的多个所述第二直线部不具有所述下部栅极导电部。
10.根据权利要求1～9中任一项所述的半导体装置，其特征在于，所述虚设沟槽部的所述下部栅极导电部设置于比所述基区靠近下方的位置。
11.根据权利要求1～10中任一项所述的半导体装置，其特征在于，所述虚设沟槽部具有：
上部绝缘膜，其设置于所述上部虚设导电部的侧部和底部；以及
下部绝缘膜，其设置于所述下部栅极导电部的侧部和底部，且比所述上部绝缘膜厚。
12.根据权利要求11所述的半导体装置，其特征在于，所述半导体基板在比所述基区靠近下方的位置具有第一导电型的漂移区，
所述虚设沟槽部的所述上部绝缘膜不与所述漂移区接触，
所述虚设沟槽部的所述下部绝缘膜与所述漂移区接触。
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