CN109564939A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109564939A
CN109564939A CN201780047373.6A CN201780047373A CN109564939A CN 109564939 A CN109564939 A CN 109564939A CN 201780047373 A CN201780047373 A CN 201780047373A CN 109564939 A CN109564939 A CN 109564939A
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semiconductor device
well region
conductive type
region
injection rate
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CN109564939B (zh
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松井俊之
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

提供一种半导体装置，具备晶体管部和二极管部，晶体管部具有：第一导电型的漂移区，形成在半导体基板的内部；第二导电型的基区，在半导体基板的内部设置在漂移区的上方；以及第二导电型的集电区，在半导体基板的内部设置在漂移区的下方，半导体装置具有第二导电型的阱区，所述第二导电型的阱区在半导体基板的内部，设置到比基区靠下方的位置为止，半导体装置在阱区的下方的至少一部分区域，具有单位面积的第二导电型的载流子注入量比集电区小的注入量限制部。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
已知具有多个单元阵列的功率IGBT(绝缘栅双极型晶体管)。在单元密度比其他单元阵列区低的单元阵列区中，被注入的空穴(hole)难以通过源电极而去除。由此，空穴的电流密度变高，会成为闩锁动作的原因。因此，已知使低密度的单元阵列区中的基板的背面侧的P型的掺杂浓度比其他单元阵列区中的基板的背面侧的P型的掺杂浓度低，或向低密度的单元阵列区中的基板的背面侧掺入N型的掺杂剂而防止闩锁的技术(例如，参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2012-182470号公报
发明内容
技术问题
在具备比晶体管部的基区深的阱区的半导体装置中，在设置深的阱区的部分的耐压变低。特别地，在像反向导通型绝缘栅双极型晶体管(RC-IGBT)那样具有晶体管部和二极管部的半导体装置中，设置深的阱区的部分与高耐压的二极管部之间的耐压差变大。因此，为了提高整个半导体装置的耐压，期望提高在设置深的阱区的部分的耐压。
技术方案
在本发明的第一形态中，提供具备晶体管部和二极管部的半导体装置。晶体管部可以具有第一导电型的漂移区、第二导电型的基区和第二导电型的集电区。漂移区可以形成在半导体基板的内部。基区可以在半导体基板的内部设置在漂移区的上方。集电区可以在半导体基板的内部设置在漂移区的下方。半导体装置可以具有第二导电型的阱区。第二导电型的阱区可以在半导体基板的内部，设置到比基区靠下方的位置为止。半导体装置可以在阱区的下方的至少一部分区域具有注入量限制部。注入量限制部的单位面积的第二导电型的载流子注入量可以比集电区小。
晶体管部可以包括绝缘栅双极晶体管。二极管部可以包括与绝缘栅双极晶体管电连接的续流二极管。
半导体装置可以具有信号焊盘区。信号焊盘区可以与晶体管部或二极管部邻接。信号焊盘区可以具有绝缘膜。绝缘膜可以形成在半导体基板的正面。信号焊盘区可以具有导电部。导电部可以形成在绝缘膜上。阱区可以设置在导电部的下方。
注入量限制部可以包括第一导电型的导电层。第一导电型的导电层可以在阱区的下方设置在与集电区相同的深度。
第一导电型的导电层可以具有比漂移区中的第一导电型的掺杂浓度高的第一导电型的掺杂浓度。
注入量限制部可以包括第二导电型的导电层。第二导电型的导电层可以设置在阱区的下方。第二导电型的导电层可以具有比集电区中的第二导电型的掺杂浓度低的第二导电型的掺杂浓度。
晶体管部可以具有背面电极。背面电极可以设置于半导体基板的背面而与集电区电连接。注入量限制部可以包括绝缘膜。绝缘膜可以设置在半导体基板与背面电极之间。
阱区可以具有比基区的第二导电型的掺杂浓度高的第二导电型的掺杂浓度。
注入量限制部可以设置在阱区的下方整个区域。
注入量限制部可以设置在晶体管部与二极管部与信号焊盘区的边界点的下方。
应予说明，上述发明概要未列举本发明的所有必要特征。另外，这些特征组的子组合也能够成为发明。
附图说明
图1是示意性地示出本发明的实施方式的半导体装置100的正面的图。
图2是示出图1中的A-A’截面的一例的图。
图3是示出图1中的B-B’截面的一例的图。
图4是示出图1中的C-C’截面的一例的图。
图5是示出比较例中的半导体装置300的截面的一例的图。
图6是示出关于本发明的实施方式的半导体装置100中的传导电流的分布与碰撞电离率的分布的模拟结果的图。
图7是示出关于比较例的半导体装置300中的传导电流的分布与碰撞电离率的分布的模拟结果的图。
图8是示出P+阱区110与集电区22之间的位置关系的图。
图9是示出注入量限制部28的宽度w与P+阱区110的端部112的温度之间的关系的一例的图。
图10是示出本发明的第二实施方式的半导体装置100的C-C’截面的一例的图。
图11是示出本发明的第三实施方式的半导体装置100的C-C’截面的一例的图。
图12是示出本发明的第四实施方式的半导体装置100的C-C’截面的一例的图。
符号说明
10：半导体基板，12：发射区，14：基区，15：接触区，18：漂移区，20：缓冲区，21：第一缓冲区，22：集电区，23：第二缓冲区，24：背面电极，27：绝缘膜，28：注入量限制部，29：导电层，30：沟槽栅极，32：栅极绝缘膜，33：栅极沟槽，34：栅极导电部，38：层间绝缘膜，40：沟槽部，42：沟槽绝缘膜，43：沟槽，44：沟槽导电部，50：边缘终止结构，52：发射电极，54：导电部，56：绝缘膜，70：晶体管部，80：二极管部，82：阴极区，90：信号焊盘区，91：焊盘区，92：焊盘区，93：焊盘区，94：栅极用焊盘区，95：温度传感器布线区，96：栅极流道区，97：边界点，100：半导体装置，110：P+阱区，112：端部，114：端部，116：端部，201：区块，202：区块，203：区块，204：区块，205：区块，211：区块，212：区块，213：区块，214：区块，215：区块，216：区块，300：半导体装置
具体实施方式
以下，通过发明的实施方式对本发明进行说明，但以下实施方式并不限定权利要求书所涉及的发明。此外，实施方式中所说明的特征的全部组合未必是发明的技术方案所必须的。
在本例中，X轴和Y轴是在与半导体基板的上表面平行的面内相互垂直的轴。此外，将与X轴和Y轴垂直的轴设为Z轴。应予说明，在本说明书中，有时将与Z轴平行的方向称为半导体基板的深度方向。
应予说明，在本说明书中，“上”、“下”、“上方”和“下方”的术语不限于重力方向上的上下方向。这些术语只不过是指相对于预定的轴的相对方向。
在本说明书和附图中，在记载了N或P的层和区域中，分别表示电子或空穴为多数载流子。另外，标记于N或P的+和-分别表示杂质浓度比未标记+和-的层或区域的杂质浓度高和低。
图1是示意性地示出本发明的实施方式的半导体装置100的正面的图。本例的半导体装置100是具备晶体管部70和二极管部80的半导体芯片。晶体管部70可以包括绝缘栅双极晶体管。二极管部80可以包括电连接于绝缘栅双极晶体管(IGBT)的续流二极管(FWD)。
晶体管部70和二极管部80可以在有源区周期性地形成。二极管部80在半导体基板的正面与晶体管部70邻接地设置。FWD反向并联连接于IGBT。半导体装置100可以具备包围有源区的边缘终止结构50。边缘终止结构50具有保护环、场板、降低表面场和将他们进行组合而成的结构中的一种以上。半导体装置100具备与晶体管部70或二极管部80邻接的信号焊盘区90。在半导体装置100中，可以存在晶体管部70与二极管部80与信号焊盘区90的边界点97。图1示出边界点97的一例。
信号焊盘区90具备形成在半导体基板的正面的绝缘膜、形成在绝缘膜上的导电部和在半导体基板的内部设置在导电部的下方的第二导电型的阱区。作为一例，半导体基板可以是Si基板，也可以是碳化硅SiC和氮化镓GaN等化合物半导体基板。作为一例，绝缘膜可以是氧化硅膜等氧化膜或氮化硅膜等氮化膜。作为一例，导电部由金属材料形成。信号焊盘区90只要是形成有这样的绝缘膜、导电部和阱区的区域即可，作为导电部还包括形成有焊盘以外的布线的区域。作为一例，信号焊盘区90可以包括传感器用焊盘区91、92、93；栅极用焊盘区94；温度传感器布线区95和栅极流道区96中的至少一个。
传感器用的焊盘区91、92是形成有温度检测部用的焊盘的区域。传感器用的焊盘区93是形成有电流检测用的焊盘的区域。栅极用焊盘区94是形成与晶体管部70的栅极金属层连接的栅极焊盘的区域。温度传感器布线区95可以是形成温度传感器自身的区域，也可以是形成与温度传感器连接的布线的区域。栅极流道区96是形成与晶体管部70的栅极金属层连接的栅极流道的区域。
图2是示出图1中的A-A’截面的一例的图。图2示出晶体管部70的结构的一例。晶体管部70具备发射区12、基区14、接触区15、漂移区18、缓冲区20、集电区22、背面电极24和沟槽栅极30。作为晶体管部70的定义，是在有源区中，与半导体基板10的背面垂直地将集电区22相对于正面侧进行投影时的投影区域，且是规则地配置有包括发射区12和接触区15的预定的单位结构。
漂移区18形成在半导体基板10的内部。漂移区18是N-型。在本例中，将第一导电型设为N型，将第二导电型设为P型。但是，在其他例中，也可以将第一导电型设为P型，将第二导电型设为N型。集电区22在半导体基板10的内部设置在漂移区18的下方。集电区22是P型。在本例中，在漂移区18的下表面设置N型的缓冲区20。缓冲区20的掺杂浓度可以比漂移区18的掺杂浓度高。缓冲区20也可以作为场截止层而发挥功能。场截止层防止从基区14的下表面扩展的耗尽层到达集电区22。集电区22可以设置在缓冲区20的下表面。
基区14在半导体基板10的内部设置在漂移区18的上方。基区14是P型。发射区12在半导体基板10的内部设置在基区14的上方。在基区14的正面可以形成有接触区15。接触区15可以是掺杂浓度比基区14高的P+型。接触区15降低基区14与发射电极52之间的接触电阻。
沟槽栅极30从半导体基板10的正面贯通基区14而到达漂移区18。在晶体管部70，多个沟槽栅极30以预定的间隔而设置。沟槽栅极30具有设置于半导体基板10的栅极沟槽33、栅极绝缘膜32和栅极导电部34。栅极绝缘膜32覆盖栅极沟槽33的内壁而设置。栅极绝缘膜32可以通过对栅极沟槽33的内壁的半导体进行氧化或氮化而形成。
栅极导电部34在栅极沟槽33的内部设置在比栅极绝缘膜32更靠内侧的位置。即，栅极绝缘膜32将栅极导电部34与半导体基板10进行绝缘。栅极导电部34由多晶硅等导电材料形成。栅极沟槽33在半导体基板10的正面被层间绝缘膜38覆盖。发射电极52位于半导体基板10的正面和层间绝缘膜38上。层间绝缘膜38将发射电极52与沟槽栅极30之间电绝缘。发射电极52由金属等导电材料形成。
沟槽栅极30内的栅极导电部34经由形成在栅极流道区96的栅极流道而与栅极金属层电连接。背面电极24设置在半导体基板10的背面。背面电极24可以与P+型的集电区22接触。背面电极24与P+型的集电区22电连接而作为集电极电极发挥功能。背面电极24由金属等导电材料形成。
图3是示出图1中的B-B’截面的一例的图。图3示出二极管部80的结构的一例。上述P型的基区14、漂移区18、缓冲区20、层间绝缘膜38和发射电极52从晶体管部70设置到二极管部80。二极管部80具备沟槽部40和阴极区82。在二极管部80未设置N+型的发射区12和P+型的接触区15。
应予说明，作为二极管部80的定义，是在有源区中，与阴极区82一致的背面区域，或与半导体基板的背面垂直地将阴极区82相对于正面侧进行投影时的投影区域。P型的基区14在半导体基板10的内部设置在漂移区18的上方。在二极管部80，P型的基区14兼做FWD的P型的阳极区。此外，发射电极52的一部分兼做阳极电极，与基区14接触。
沟槽部40从半导体基板10的正面贯通基区14(阳极区)而到达漂移区18。在二极管部80，多个沟槽部40以预定的间隔而设置。沟槽部40具有设置于半导体基板10的沟槽43、沟槽绝缘膜42和沟槽导电部44。沟槽绝缘膜42覆盖沟槽43的内壁而设置。沟槽绝缘膜42可以通过对沟槽43的内壁的半导体进行氧化或氮化而形成。
沟槽导电部44在沟槽43的内部设置在比沟槽绝缘膜42更靠内侧的位置。沟槽绝缘膜42将沟槽导电部44与半导体基板10进行绝缘。沟槽导电部44由多晶硅等导电材料形成。沟槽部40内的沟槽导电部44不与栅极流道连接。沟槽导电部44通过接触孔等与作为阳极电极而发挥功能的发射电极52电连接。二极管部80在半导体基板10的内部在漂移区18的下方具备阴极区82。阴极区82是N+型。阴极区82设置在缓冲区20的下表面。
半导体装置100具有周期性地配置有图2和图3所示的晶体管部70和二极管部80而成的结构。在晶体管部70中的多个沟槽栅极30等的间距宽的情况下，有源区的等势面也依赖于沟槽栅极30而周期性地变化，沟槽栅极30的底部的电场强度变高。因此，由于沟槽栅极30的底部的部分的耐压变低，所以多数情况下半导体装置100整体的耐压也由有源区内的耐压决定。然而，如果将沟槽栅极30的间距微细化，则等势面不会大幅变化，因此在有源区的耐压变高。因此，产生信号焊盘区90中的耐压决定半导体装置100整体的耐压的情况。因此，本例的半导体装置100提高信号焊盘区90中的耐压而提高半导体装置100整体的耐压。
图4是示出图1中的C-C’截面的一例的图。图4主要示出信号焊盘区90中的结构。信号焊盘区90具有绝缘膜56、导电部54和P+阱区110。P+阱区110可以与发射电极52电连接而被施加发射极电位。此外，信号焊盘区90可以具有上述漂移区18和背面电极24。因此，漂移区18和背面电极24可以遍及信号焊盘区90和晶体管部70而扩展。
绝缘膜56形成在半导体基板10的正面。绝缘膜56可以与图2中说明的栅极绝缘膜32一体地形成。在此情况下，绝缘膜56与栅极绝缘膜32可以是相同材料，也可以与栅极绝缘膜32具有相同的厚度。绝缘膜56可以通过对半导体基板10的正面进行氧化或氮化而形成。导电部54隔着绝缘膜56设置于半导体基板10的正面。导电部54可以由金属或多晶硅等导电性材料形成。在本例中，导电部54是铝等金属膜。导电部54既可以是焊盘层，也可以是布线，还可以是传感器部。
P+阱区110在半导体基板10的内部设置在导电部54的下方。P+阱区110可以从半导体基板10的正面朝向下方而形成。P+阱区110设置到比晶体管部70中的基区14更靠下方的位置为止。即，P+阱区110在半导体基板10的厚度方向(Z轴方向)上的深度可以比晶体管部70中的基区14深。P+阱区110可以具有比晶体管部70中的P型的基区14的P型的掺杂浓度高的P+型的掺杂浓度。
在P+阱区110的下方的至少一部分区域，半导体装置100具有单位面积的第二导电型的载流子注入量比集电区22小的注入量限制部28。在本例中，注入量限制部28包括在P+阱区110的下方设置在与集电区22相同深度的N型的导电层。相同深度不仅包括在半导体基板10的厚度方向(Z轴方向)上的、各自的正面和背面一致的情况，还包括区域共同存在于半导体基板10的厚度方向(Z轴方向)的任意位置的情况。
在本例中，作为N型的导电层而设置缓冲区20。信号焊盘区90中的缓冲区20可以包括第一缓冲区21和第二缓冲区23。第一缓冲区21设置在与晶体管部70中的缓冲区20相同的深度。第二缓冲区23设置在与集电区22相同深度而与背面电极24接触。
在P+阱区110的下方设置在与集电区22相同深度的N型的导电层可以具有比漂移区18中的N型的掺杂浓度高的N型的掺杂浓度。在本例中，第二缓冲区23的N型的掺杂浓度比漂移区18中的N型的掺杂浓度高。由此，能够降低N型的导电层与背面电极24之间的接触电阻。第一缓冲区21和第二缓冲区23双方的N型的掺杂浓度可以比漂移区18的N型的掺杂浓度高。
设置在与集电区22相同深度的N型的导电层不限于缓冲区20。在半导体装置100不具有缓冲区20的情况下，漂移区18可以是设置在与集电区22相同深度的N型的导电层。
在本例中，注入量限制部28设置在P+阱区110的下方整个区域。注入量限制部28可以被划分为在俯视时至少包含P+阱区110。在俯视时，注入量限制部28的端部114的位置可以与P+阱区110的端部112的位置一致。俯视是指从半导体基板10的正面观察的情况。
根据本例，设置有P+阱区110。能够通过P+阱区110降低电阻率。通过降低电阻率，电流流通时的电压降(电动势)也变低。因此，在从相邻的晶体管部70沿着绝缘膜56的平行面(XY平面)而流通电流的情况下产生的电动势也变低，所以能够防止信号焊盘区90的绝缘膜56受到损伤。
由于P+阱区110形成得比晶体管部70中的基区14深，所以在设置P+阱区110的信号焊盘区90的耐压容易变低。然而，根据本例的半导体装置100，在P+阱区110的下方的区域不存在集电区22。换言之，半导体装置100在P+阱区110的下方的至少一部分区域具有注入量限制部28，所述注入量限制部28的单位面积的第二导电型的载流子注入量比集电区22小。
如果从背面电极24向P+阱区110的下方区域注入的第二导电型的载流子的注入量减小，则耐压变高。在半导体基板10的内部，耗尽层容易向没有载流子的部分扩展。因此，如果从背面电极24注入第二导电型的载流子，则耗尽层变得难以扩展。由此，在从背面电极24注入第二导电型的载流子的情况下的耐压与没有注入载流子的情况下的耐压相比降低。相反地，如果局部地形成没有从背面电极24注入第二导电型的载流子的部分，则耗尽层扩展。因此，在该部分处耐压变高。
根据本例的半导体装置100，在因P+阱区110的存在而使得耐压容易变低的区域中，抑制第二导电型的载流子的注入。因此，能够提高因P+阱区110的存在而使得耐压容易变低的区域中的耐压。由此，能够减小在半导体装置100内的耐压差，并提高半导体装置100内的耐压。
注入量限制部28也可以不一定设置在信号焊盘区90的整体。注入量限制部28可以至少设置在晶体管部70与二极管部80与信号焊盘区90的边界点97的下方。特别地，在半导体装置100为RC-IGBT的情况下，由于没有来自背面电极24侧的载流子的注入的二极管部80的耐压高，所以容易在图1所示的边界点97产生耐压差。通过在边界点97的下方设置注入量限制部28，从而能够减小在半导体装置100内的耐压差。
对本例的半导体装置100的制造方法的一例进行说明。首先，在半导体装置100的正面，形成发射区12和基区14等掺杂区。此外，还形成P+阱区110等掺杂区。发射区12可以通过注入磷等掺杂剂而形成。基区14可以通过注入硼等掺杂剂而形成。P+阱区110可以通过注入硼等掺杂剂而形成。此外，在形成了掺杂区之后，形成沟槽栅极30等。然后，形成覆盖各沟槽栅极30的层间绝缘膜38。
接下来，形成发射电极52。发射电极52可以通过溅射而形成。溅射时，可以将半导体基板10的温度设为350℃至450℃左右。接下来，对半导体基板10的与正面相反侧的面进行研磨，而调整半导体基板10的厚度。半导体基板10的厚度根据半导体装置100所应具有的耐压而设定。
接下来，形成半导体装置100的背面结构。下表面结构例如是集电区22和阴极区82。集电区22可以通过注入硼等P型掺杂剂而形成。在形成集电区22时，可以形成掩模，以使得不在与P+阱区110的下方相当的区域，即信号焊盘区90注入硼等P型掺杂剂。其结果是，在P+阱区110的下方不形成集电区22。接下来，从半导体基板10的背面注入质子而形成缓冲区20。对半导体基板10进行退火而使注入到缓冲区20的质子活化。
对如上所述地构成的本例的半导体装置100的效果进行说明。为了说明本例的半导体装置100的效果而参照比较例。图5是示出比较例中的半导体装置300的截面的一例的图。在半导体装置300中，P型的集电区22设置到P+阱区110的下方为止。
图6是示出关于本发明的实施方式的半导体装置100中的传导电流的分布与碰撞电离率的分布的模拟结果的图。图6的上部分示出进行了电压钳位的状态下的传导电流的分布。图6的下部分示出进行了电压钳位的状态下的碰撞电离率的分布。同样地，图7是示出关于比较例的半导体装置300中的传导电流的分布与碰撞电离率的分布的模拟结果的图。在图6和图7中，纵轴表示深度方向(Z轴方向)，横轴表示半导体基板10的正面的面内方向(X方向)。
区块201表示传导电流最小的区块，按区块201、区块202、区块203、区块204和区块205的顺序，传导电流变大。区块205表示传导电流最大。如图7所示，在比较例的半导体装置300中，存在P+阱区110的信号焊盘区90中的传导电流示出最大值的区块205。与此相对，如图6所示，在本例的半导体装置100中，存在P+阱区110的信号焊盘区90中的传导电流示出区块201和区块202。
关于成为雪崩现象等击穿的指标的碰撞电离率，区块211表示碰撞电离率最低的区块，按区块211、区块212、区块213、区块214、区块215和区块216的顺序，碰撞电离率变大。区块216表示碰撞电离率最高。如图7所示，在比较例的半导体装置300中。存在P+阱区110的信号焊盘区90中的碰撞电离率示出最高值的区块216。与此相对，如图6所示，在本例的半导体装置100中，存在P+阱区110的信号焊盘区90中的碰撞电离率示出区块211和区块212。
图7所示的比较例的半导体装置300在存在P+阱区110的信号焊盘区90中，碰撞电离率示出高值，因此，示出发生了雪崩现象。其结果是，在比较例的半导体装置300中，电流集中于存在P+阱区110的区域。另一方面，在图6所示的本实施方式的半导体装置100中，防止了雪崩现象，能够避免电流向存在P+阱区110的区域集中。
图8是示出P+阱区110与集电区22之间的位置关系的图。在本例中，作为一例，示出了通过使用宽度为36.5μm的掩模进行离子注入，并在离子注入后进行退火处理来形成P+阱区110的情况。P+阱区110的宽度d包含因退火处理引起的扩散部分而被设定为预定的值。在本例中，P+阱区110的宽度d为43μm。注入量限制部28的宽度w与没有集电区22的部分的宽度对应。
在注入量限制部28的宽度w比P+阱区110的宽度d小的情况下，集电区22扩展到P+阱区110的下方的区域为止。因此，在俯视时集电区22与P+阱区110重叠。并且，随着注入量限制部28的宽度w以接近P+阱区110的宽度d的方式增加，在俯视时集电区22与P+阱区110重叠的部分变小。在注入量限制部28的宽度w为P+阱区110的宽度d以上的情况下，在P+阱区110的下方的整个区域，没有集电区22。换言之，注入量限制部28设置在P+阱区110的下方整个区域。在此情况下，在俯视时集电区22与P+阱区110不重叠。
图9是示出注入量限制部28的宽度w与P+阱区110的端部112的温度之间的关系的一例的图。在注入量限制部28的宽度w为零的情况下，即，P型的集电区22设置在P+阱区110的下方整个区域的情况下，P+阱区110的端部112的温度上升到200℃左右。这与图5所示的比较例的半导体装置300对应。因电流集中于存在P+阱区110的区域，所以产生温度上升。
随着注入量限制部28的宽度w以接近P+阱区110的宽度d的方式增加，P+阱区110的端部112的温度减小。即，随着在俯视时集电区22与P+阱区110重叠的部分变小，P+阱区110的端部112的温度减小。并且，如果注入量限制部28的宽度w达到P+阱区110的宽度d，则在俯视时集电区22与P+阱区110不重叠，P+阱区110的端部112的温度示出最低值。
根据本例，在注入量限制部28的宽度w为P+阱区110的宽度d的60％的情况下，即，注入量限制部28设置在P+阱区110的下方区域的60％的区域的情况下，能够将P+阱区110的端部112的温度抑制为100℃以下。在注入量限制部28的宽度w为P+阱区110的宽度d的90％的情况下，即，注入量限制部28设置在P+阱区110的下方区域的90％的区域的情况下，能够将P+阱区110的端部112的温度抑制为50℃以下。进一步地，在注入量限制部28的宽度w为P+阱区110的宽度d以上的情况下，即，注入量限制部28设置在P+阱区110的下方整个区域的情况下，P+阱区110的端部112的温度能够抑制为室温左右。因此，注入量限制部28优选设置在将P+阱区110投影到半导体基板10的背面时的投影区域的60％以上的区域，更优选设置在投影区域的90％以上的区域，进一步优选设置在投影区域的90％以上的整个区域。
根据本例的半导体装置100，能够抑制因电流集中引起的发热，并将伴随着发热的信号焊盘区90的损伤防患于未然。特别地，能够将因电流集中引起的发热所导致的绝缘膜56的损伤防患于未然。其结果是能够改善耐量。此外，由于仅在信号焊盘区90不设置集电区22，所以对晶体管部70中的IGBT特性的影响小。
图10是示出本发明的第二实施方式的半导体装置100的C-C’截面的一例的图。在第一实施方式的半导体装置100中，说明了包括在P+阱区110的下方设置于与集电区22相同深度的第一导电型的导电层的情况。与此相对，在本例中，注入量限制部具备在P+阱区110的下方设置的第二导电型的导电层29。第二导电型的导电层29具有比集电区22中的第二导电型的掺杂浓度低的比P型的掺杂浓度低的第二导电型的掺杂浓度。导电层29是P型。
在本例中，作为注入量限制部而发挥功能的第二导电型的导电层29设置在P+阱区110的下方整个区域。第二导电型的导电层29可以被划分为在俯视时至少包含P+阱区110。在俯视时，导电层29的端部的位置可以与P+阱区110的端部112的位置一致。在本例中，导电层29设置在与集电区22相同的深度。导电层29可以与背面电极24接触。除了注入量限制部的结构以外，本例的半导体装置100与第一实施方式的半导体装置100的结构相同。因此，省略重复说明。
本例的半导体装置100能够通过各种制造方法来制造。例如，在形成半导体装置100的背面结构时，注入P型掺杂剂，以使集电区22和与P+阱区110的下方相当的区域(即，信号焊盘区90)共同成为第一掺杂浓度。接下来，形成覆盖与P+阱区110的下方相当的区域，即信号焊盘区90的掩模。接下来，可以对集电区22追加注入P型掺杂剂而成为比第一掺杂浓度高的第二掺杂浓度。通过这样的制造方法能够制造第二实施方式的半导体装置100。
在本例的半导体装置100中，导电层29的第二导电型的P型掺杂剂的掺杂浓度比集电区22低。由于P型掺杂剂的掺杂浓度的差异，使得导电层29的单位面积的第二导电型的载流子注入量比集电区22小。因此，导电层29作为注入量限制部而发挥功能。根据本例，由于向设置有P+阱区110的部分注入的第二导电型的载流子的注入量降低，所以能够提高耐压。
图11是示出本发明的第三实施方式的半导体装置100的C-C’截面的一例的图。在本例中，注入量限制部包括在P+阱区110的下方设置在半导体基板10与背面电极24之间的绝缘膜27。作为一例，绝缘膜27由氧化硅膜等氧化膜或氮化硅膜等氮化膜形成。
在本例中，作为注入量限制部而发挥功能的绝缘膜27设置在P+阱区110的下方整个区域。绝缘膜27可以被划分为在俯视时至少包含P+阱区110。在俯视时，绝缘膜27的端部116的位置可以与P+阱区110的端部112的位置一致。在本例中，P型的集电区22可以设置到P+阱区110的下方为止。绝缘膜27可以以与集电区22接触的方式设置。除了注入量限制部的结构以外，本例的半导体装置100与第一实施方式和第二实施方式的半导体装置100的结构相同。因此，省略重复说明。
本例的半导体装置100能够通过各种制造方法来制造。例如，在半导体装置100的背面形成集电区22之后，在集电区22形成绝缘膜。对绝缘膜进行图案化而在信号焊盘区90保留绝缘膜27。由此，在晶体管部70，露出集电区22。以覆盖露出的集电区22和绝缘膜27的方式形成背面电极24。可以根据需要将背面电极24进行平坦化。绝缘膜27与背面电极24之间不导电。因此，在设置有绝缘膜27的区域中，也可以不设置背面电极24。
根据本例的半导体装置100，第二导电型的载流子向设置有P+阱区110的部分的注入被绝缘膜27限制。因此，通过本例也能够提高耐压。
图12是示出本发明的第四实施方式的半导体装置100的C-C’截面的一例的图。在本例中，注入量限制部28包括在P+阱区110的下方设置在与集电区22相同深度的N型的导电层。在本例中，作为N型的导电层，设置缓冲区20。在本例中，设置有注入量限制部28的区域比将P+阱区110投影到半导体基板10的背面时的投影区域大。其结果是，注入量限制部28的端部114与P+阱区110的端部112相比更位于晶体管部70侧。因此，在晶体管部70中也局部地具有不存在集电区22的部分。注入量限制部28的端部114(集电区22的端部)与P+阱区110的端部112在俯视时分开了距离Q。距离Q可以是0μm以上且50μm以下。如果距离Q为50μm以上，则有时会对晶体管部70的特性带来影响，因此，距离Q优选为50μm以下。
以上，使用实施方式对本发明进行了说明，但是本发明的技术范围并不限于上述实施方式所记载的范围。各实施方式可以进行组合。可以对上述实施方式追加各种变更或改进的情况对本领域技术人员来说是显而易见的。从权利要求书的记载可知，追加了那样的变更或改进的方式也可以包括在本发明的技术范围内。
应注意，权利要求书、说明书及附图中示出的装置、系统、程序及方法中的动作、过程、步骤和阶段等各处理的执行顺序只要未特别明示“早于”、“预先”等，另外，未在后续处理中使用之前的处理结果，则可以以任意顺序来实现。关于权利要求书、说明书及附图中的动作流程，即使为方便起见使用“首先”、“接下来”等进行了说明，也并不意味着必须以这一顺序来实施。

Claims (10)

1.一种半导体装置，其特征在于，所述半导体装置具备晶体管部和二极管部，
所述晶体管部具有：
第一导电型的漂移区，形成在半导体基板的内部；
第二导电型的基区，在所述半导体基板的内部设置在所述漂移区的上方；以及
第二导电型的集电区，在所述半导体基板的内部设置在所述漂移区的下方，
所述半导体装置具有第二导电型的阱区，所述第二导电型的阱区在所述半导体基板的内部，设置到比所述基区靠下方的位置为止，
所述半导体装置在所述阱区的下方的至少一部分区域具有注入量限制部，所述注入量限制部的单位面积的第二导电型的载流子注入量比所述集电区的单位面积的第二导电型的载流子注入量小。
2.根据权利要求1所述的半导体装置，其特征在于，
所述晶体管部包括绝缘栅双极晶体管，
所述二极管部包括与所述绝缘栅双极晶体管电连接的续流二极管。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体装置具有与所述晶体管部或所述二极管部邻接的信号焊盘区，
所述信号焊盘区具有：
绝缘膜，形成在所述半导体基板的正面；以及
导电部，形成在所述绝缘膜上，
所述阱区设置在所述导电部的下方。
4.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
所述注入量限制部包括第一导电型的导电层，所述第一导电型的导电层在所述阱区的下方设置在与所述集电区相同的深度。
5.根据权利要求4所述的半导体装置，其特征在于，
所述第一导电型的导电层具有比所述漂移区中的第一导电型的掺杂浓度高的第一导电型的掺杂浓度。
6.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
所述注入量限制部包括在所述阱区的下方设置的第二导电型的导电层，
所述第二导电型的导电层具有比所述集电区中的第二导电型的掺杂浓度低的第二导电型的掺杂浓度。
7.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
所述晶体管部还具备背面电极，所述背面电极设置于所述半导体基板的背面而与所述集电区电连接，
所述注入量限制部包括设置在所述半导体基板与所述背面电极之间的绝缘膜。
8.根据权利要求1～7中任一项所述的半导体装置，其特征在于，
所述阱区具有比所述基区的第二导电型的掺杂浓度高的第二导电型的掺杂浓度。
9.根据权利要求1～8中任一项所述的半导体装置，其特征在于，
所述注入量限制部设置在所述阱区的下方整个区域。
10.根据权利要求3所述的半导体装置，其特征在于，
所述注入量限制部设置在所述晶体管部与所述二极管部与所述信号焊盘区的边界点的下方。
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