JP2017520786A5 - - Google Patents
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- Publication number
- JP2017520786A5 JP2017520786A5 JP2016567854A JP2016567854A JP2017520786A5 JP 2017520786 A5 JP2017520786 A5 JP 2017520786A5 JP 2016567854 A JP2016567854 A JP 2016567854A JP 2016567854 A JP2016567854 A JP 2016567854A JP 2017520786 A5 JP2017520786 A5 JP 2017520786A5
- Authority
- JP
- Japan
- Prior art keywords
- cells
- integrated circuit
- functional
- array
- lithography
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 26
- 238000009792 diffusion process Methods 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 7
- 238000000609 electron-beam lithography Methods 0.000 claims 4
- 238000001900 extreme ultraviolet lithography Methods 0.000 claims 4
- 238000001459 lithography Methods 0.000 claims 4
- 238000005530 etching Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000001127 nanoimprint lithography Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003068 static effect Effects 0.000 claims 1
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2014/044105 WO2015199682A1 (en) | 2014-06-25 | 2014-06-25 | Techniques for forming a compacted array of functional cells |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017520786A JP2017520786A (ja) | 2017-07-27 |
| JP2017520786A5 true JP2017520786A5 (enExample) | 2017-09-07 |
| JP6415602B2 JP6415602B2 (ja) | 2018-10-31 |
Family
ID=54938598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016567854A Active JP6415602B2 (ja) | 2014-06-25 | 2014-06-25 | 機能セルのコンパクトアレイを形成するための技術 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10217732B2 (enExample) |
| EP (1) | EP3161854A4 (enExample) |
| JP (1) | JP6415602B2 (enExample) |
| KR (1) | KR20170026336A (enExample) |
| CN (1) | CN106463354B (enExample) |
| TW (1) | TWI565018B (enExample) |
| WO (1) | WO2015199682A1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106463354B (zh) | 2014-06-25 | 2019-12-20 | 英特尔公司 | 用于形成功能单元的紧凑阵列的技术 |
| KR102217246B1 (ko) * | 2014-11-12 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
| US9577639B1 (en) * | 2015-09-24 | 2017-02-21 | Qualcomm Incorporated | Source separated cell |
| US10109582B2 (en) * | 2016-04-19 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company Limited | Advanced metal connection with metal cut |
| KR101958518B1 (ko) * | 2016-08-09 | 2019-03-15 | 매그나칩 반도체 유한회사 | 프로그래밍의 신뢰성이 개선된 otp 셀 |
| CN107480359B (zh) * | 2017-08-02 | 2021-04-30 | 复旦大学 | 先进纳米工艺下fpga面积建模方法 |
| US10790395B2 (en) | 2018-06-12 | 2020-09-29 | International Business Machines Corporation | finFET with improved nitride to fin spacing |
| CN110267186A (zh) * | 2019-05-27 | 2019-09-20 | 深圳市中德听力技术有限公司 | 一种具有内置纯音信号发生器的自我验配助听器 |
| CN110299356A (zh) * | 2019-07-26 | 2019-10-01 | 宁波芯浪电子科技有限公司 | 一种用于mos管的静电保护方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05298394A (ja) | 1992-04-23 | 1993-11-12 | Hitachi Ltd | 自動配置方法 |
| US6911730B1 (en) | 2003-03-03 | 2005-06-28 | Xilinx, Inc. | Multi-chip module including embedded transistors within the substrate |
| US8658542B2 (en) * | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US20090255801A1 (en) * | 2008-04-11 | 2009-10-15 | Haas Alfred M | Programmable Electrode Arrays and Methods for Manipulating and Sensing Cells and Substances Using Same |
| JP5167050B2 (ja) | 2008-09-30 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法およびマスクの製造方法 |
| US8631374B2 (en) * | 2011-03-30 | 2014-01-14 | Synopsys, Inc. | Cell architecture for increasing transistor size |
| JP2013149928A (ja) * | 2012-01-23 | 2013-08-01 | Canon Inc | リソグラフィー装置および物品を製造する方法 |
| JP6087506B2 (ja) * | 2012-01-31 | 2017-03-01 | キヤノン株式会社 | 描画方法及び物品の製造方法 |
| US9012287B2 (en) | 2012-11-14 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell layout for SRAM FinFET transistors |
| US8839168B2 (en) * | 2013-01-22 | 2014-09-16 | Globalfoundries Inc. | Self-aligned double patterning via enclosure design |
| CN106463354B (zh) | 2014-06-25 | 2019-12-20 | 英特尔公司 | 用于形成功能单元的紧凑阵列的技术 |
-
2014
- 2014-06-25 CN CN201480079231.4A patent/CN106463354B/zh active Active
- 2014-06-25 US US15/124,817 patent/US10217732B2/en active Active
- 2014-06-25 KR KR1020167032597A patent/KR20170026336A/ko not_active Ceased
- 2014-06-25 WO PCT/US2014/044105 patent/WO2015199682A1/en not_active Ceased
- 2014-06-25 JP JP2016567854A patent/JP6415602B2/ja active Active
- 2014-06-25 EP EP14896073.5A patent/EP3161854A4/en not_active Withdrawn
-
2015
- 2015-05-18 TW TW104115775A patent/TWI565018B/zh active
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