KR20170026336A - 기능 셀들의 압축된 어레이를 형성하기 위한 기술 - Google Patents

기능 셀들의 압축된 어레이를 형성하기 위한 기술 Download PDF

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KR20170026336A
KR20170026336A KR1020167032597A KR20167032597A KR20170026336A KR 20170026336 A KR20170026336 A KR 20170026336A KR 1020167032597 A KR1020167032597 A KR 1020167032597A KR 20167032597 A KR20167032597 A KR 20167032597A KR 20170026336 A KR20170026336 A KR 20170026336A
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Prior art keywords
cells
array
boundaries
resist
lithography
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Korean (ko)
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라니 티. 엘사예드
니티 고엘
실비오 이. 보우-가잘
랜디 제이. 아크사미트
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인텔 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H01L27/0207—
    • G06F17/5068—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • H01L21/027—
    • H01L27/11—
    • H01L27/11807—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2045—Electron beam lithography processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/951—Technology used, i.e. design rules
    • H10D84/953—Sub-micron technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/959—Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/966—Gate electrode terminals or contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/975—Wiring regions or routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020167032597A 2014-06-25 2014-06-25 기능 셀들의 압축된 어레이를 형성하기 위한 기술 Ceased KR20170026336A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/044105 WO2015199682A1 (en) 2014-06-25 2014-06-25 Techniques for forming a compacted array of functional cells

Publications (1)

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KR20170026336A true KR20170026336A (ko) 2017-03-08

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US (1) US10217732B2 (enExample)
EP (1) EP3161854A4 (enExample)
JP (1) JP6415602B2 (enExample)
KR (1) KR20170026336A (enExample)
CN (1) CN106463354B (enExample)
TW (1) TWI565018B (enExample)
WO (1) WO2015199682A1 (enExample)

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WO2015199682A1 (en) 2014-06-25 2015-12-30 Intel Corporation Techniques for forming a compacted array of functional cells
KR102217246B1 (ko) * 2014-11-12 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9577639B1 (en) * 2015-09-24 2017-02-21 Qualcomm Incorporated Source separated cell
US10109582B2 (en) 2016-04-19 2018-10-23 Taiwan Semiconductor Manufacturing Company Limited Advanced metal connection with metal cut
KR101958518B1 (ko) * 2016-08-09 2019-03-15 매그나칩 반도체 유한회사 프로그래밍의 신뢰성이 개선된 otp 셀
CN107480359B (zh) * 2017-08-02 2021-04-30 复旦大学 先进纳米工艺下fpga面积建模方法
US10790395B2 (en) 2018-06-12 2020-09-29 International Business Machines Corporation finFET with improved nitride to fin spacing
CN110267186A (zh) * 2019-05-27 2019-09-20 深圳市中德听力技术有限公司 一种具有内置纯音信号发生器的自我验配助听器
CN110299356A (zh) * 2019-07-26 2019-10-01 宁波芯浪电子科技有限公司 一种用于mos管的静电保护方法

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JPH05298394A (ja) * 1992-04-23 1993-11-12 Hitachi Ltd 自動配置方法
US6911730B1 (en) * 2003-03-03 2005-06-28 Xilinx, Inc. Multi-chip module including embedded transistors within the substrate
US8658542B2 (en) * 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US20090255801A1 (en) * 2008-04-11 2009-10-15 Haas Alfred M Programmable Electrode Arrays and Methods for Manipulating and Sensing Cells and Substances Using Same
JP5167050B2 (ja) * 2008-09-30 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法およびマスクの製造方法
US8631374B2 (en) 2011-03-30 2014-01-14 Synopsys, Inc. Cell architecture for increasing transistor size
JP2013149928A (ja) * 2012-01-23 2013-08-01 Canon Inc リソグラフィー装置および物品を製造する方法
JP6087506B2 (ja) 2012-01-31 2017-03-01 キヤノン株式会社 描画方法及び物品の製造方法
US9012287B2 (en) 2012-11-14 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Cell layout for SRAM FinFET transistors
US8839168B2 (en) * 2013-01-22 2014-09-16 Globalfoundries Inc. Self-aligned double patterning via enclosure design
WO2015199682A1 (en) 2014-06-25 2015-12-30 Intel Corporation Techniques for forming a compacted array of functional cells

Also Published As

Publication number Publication date
WO2015199682A8 (en) 2016-03-17
TWI565018B (zh) 2017-01-01
CN106463354B (zh) 2019-12-20
EP3161854A4 (en) 2018-05-30
WO2015199682A1 (en) 2015-12-30
JP2017520786A (ja) 2017-07-27
US10217732B2 (en) 2019-02-26
TW201611223A (zh) 2016-03-16
EP3161854A1 (en) 2017-05-03
US20170018543A1 (en) 2017-01-19
CN106463354A (zh) 2017-02-22
JP6415602B2 (ja) 2018-10-31

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