CN106463354B - 用于形成功能单元的紧凑阵列的技术 - Google Patents

用于形成功能单元的紧凑阵列的技术 Download PDF

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CN106463354B
CN106463354B CN201480079231.4A CN201480079231A CN106463354B CN 106463354 B CN106463354 B CN 106463354B CN 201480079231 A CN201480079231 A CN 201480079231A CN 106463354 B CN106463354 B CN 106463354B
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cells
array
lines
boundaries
lithography
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CN106463354A (zh
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R·T·埃尔赛义德
N·戈埃尔
S·E·布-加扎利
R·J·阿克萨米特
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0277—Electrolithographic processes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/951—Technology used, i.e. design rules
    • H10D84/953—Sub-micron technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/959—Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/966—Gate electrode terminals or contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/975—Wiring regions or routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CN201480079231.4A 2014-06-25 2014-06-25 用于形成功能单元的紧凑阵列的技术 Active CN106463354B (zh)

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Application Number Priority Date Filing Date Title
PCT/US2014/044105 WO2015199682A1 (en) 2014-06-25 2014-06-25 Techniques for forming a compacted array of functional cells

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CN106463354B true CN106463354B (zh) 2019-12-20

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US (1) US10217732B2 (enExample)
EP (1) EP3161854A4 (enExample)
JP (1) JP6415602B2 (enExample)
KR (1) KR20170026336A (enExample)
CN (1) CN106463354B (enExample)
TW (1) TWI565018B (enExample)
WO (1) WO2015199682A1 (enExample)

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CN106463354B (zh) 2014-06-25 2019-12-20 英特尔公司 用于形成功能单元的紧凑阵列的技术
KR102217246B1 (ko) * 2014-11-12 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9577639B1 (en) * 2015-09-24 2017-02-21 Qualcomm Incorporated Source separated cell
US10109582B2 (en) * 2016-04-19 2018-10-23 Taiwan Semiconductor Manufacturing Company Limited Advanced metal connection with metal cut
KR101958518B1 (ko) * 2016-08-09 2019-03-15 매그나칩 반도체 유한회사 프로그래밍의 신뢰성이 개선된 otp 셀
CN107480359B (zh) * 2017-08-02 2021-04-30 复旦大学 先进纳米工艺下fpga面积建模方法
US10790395B2 (en) 2018-06-12 2020-09-29 International Business Machines Corporation finFET with improved nitride to fin spacing
CN110267186A (zh) * 2019-05-27 2019-09-20 深圳市中德听力技术有限公司 一种具有内置纯音信号发生器的自我验配助听器
CN110299356A (zh) * 2019-07-26 2019-10-01 宁波芯浪电子科技有限公司 一种用于mos管的静电保护方法

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US6911730B1 (en) * 2003-03-03 2005-06-28 Xilinx, Inc. Multi-chip module including embedded transistors within the substrate
US20090255801A1 (en) * 2008-04-11 2009-10-15 Haas Alfred M Programmable Electrode Arrays and Methods for Manipulating and Sensing Cells and Substances Using Same
US20100080647A1 (en) * 2008-09-30 2010-04-01 Renesas Technology Corp. Manufacturing method of semiconductor device and manufacturing method of mask
US20120254817A1 (en) * 2011-03-30 2012-10-04 Synopsys, Inc. Cell Architecture for Increasing Transistor Size
US20130188165A1 (en) * 2012-01-23 2013-07-25 Canon Kabushiki Kaisha Lithography apparatus, and method of manufacturing article
US20130196517A1 (en) * 2012-01-31 2013-08-01 Canon Kabushiki Kaisha Drawing method and method of manufacturing article
US20140131813A1 (en) * 2012-11-14 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cell Layout for SRAM FinFET Transistors
US20140167183A1 (en) * 2006-03-09 2014-06-19 Tela Innovations, Inc. Coarse Grid Design Methods and Structures

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US8839168B2 (en) * 2013-01-22 2014-09-16 Globalfoundries Inc. Self-aligned double patterning via enclosure design
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US20140167183A1 (en) * 2006-03-09 2014-06-19 Tela Innovations, Inc. Coarse Grid Design Methods and Structures
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US20100080647A1 (en) * 2008-09-30 2010-04-01 Renesas Technology Corp. Manufacturing method of semiconductor device and manufacturing method of mask
US20120254817A1 (en) * 2011-03-30 2012-10-04 Synopsys, Inc. Cell Architecture for Increasing Transistor Size
US20130188165A1 (en) * 2012-01-23 2013-07-25 Canon Kabushiki Kaisha Lithography apparatus, and method of manufacturing article
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US20170018543A1 (en) 2017-01-19
EP3161854A4 (en) 2018-05-30
WO2015199682A8 (en) 2016-03-17
JP2017520786A (ja) 2017-07-27
EP3161854A1 (en) 2017-05-03
CN106463354A (zh) 2017-02-22
JP6415602B2 (ja) 2018-10-31
WO2015199682A1 (en) 2015-12-30
KR20170026336A (ko) 2017-03-08
TWI565018B (zh) 2017-01-01
TW201611223A (zh) 2016-03-16
US10217732B2 (en) 2019-02-26

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