JP2017505530A5 - - Google Patents

Download PDF

Info

Publication number
JP2017505530A5
JP2017505530A5 JP2016532522A JP2016532522A JP2017505530A5 JP 2017505530 A5 JP2017505530 A5 JP 2017505530A5 JP 2016532522 A JP2016532522 A JP 2016532522A JP 2016532522 A JP2016532522 A JP 2016532522A JP 2017505530 A5 JP2017505530 A5 JP 2017505530A5
Authority
JP
Japan
Prior art keywords
transistor
region
voltage
gate
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016532522A
Other languages
English (en)
Japanese (ja)
Other versions
JP6219521B2 (ja
JP2017505530A (ja
Filing date
Publication date
Priority claimed from US14/225,836 external-priority patent/US9601607B2/en
Application filed filed Critical
Publication of JP2017505530A publication Critical patent/JP2017505530A/ja
Publication of JP2017505530A5 publication Critical patent/JP2017505530A5/ja
Application granted granted Critical
Publication of JP6219521B2 publication Critical patent/JP6219521B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2016532522A 2013-11-27 2014-11-13 デュアルモードトランジスタ Expired - Fee Related JP6219521B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361909533P 2013-11-27 2013-11-27
US61/909,533 2013-11-27
US14/225,836 US9601607B2 (en) 2013-11-27 2014-03-26 Dual mode transistor
US14/225,836 2014-03-26
PCT/US2014/065539 WO2015080873A1 (en) 2013-11-27 2014-11-13 Dual mode transistor

Publications (3)

Publication Number Publication Date
JP2017505530A JP2017505530A (ja) 2017-02-16
JP2017505530A5 true JP2017505530A5 (enExample) 2017-06-15
JP6219521B2 JP6219521B2 (ja) 2017-10-25

Family

ID=53182135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016532522A Expired - Fee Related JP6219521B2 (ja) 2013-11-27 2014-11-13 デュアルモードトランジスタ

Country Status (5)

Country Link
US (1) US9601607B2 (enExample)
EP (1) EP3075010B1 (enExample)
JP (1) JP6219521B2 (enExample)
CN (1) CN105793986B (enExample)
WO (1) WO2015080873A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319662B2 (en) 2017-02-01 2019-06-11 Indian Institute Of Science Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks
US10483258B2 (en) 2017-02-25 2019-11-19 Indian Institute Of Science Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity
TWI655772B (zh) * 2017-05-05 2019-04-01 旺宏電子股份有限公司 半導體元件
US10256307B2 (en) 2017-05-08 2019-04-09 Macronix International Co., Ltd. Semiconductor device
CN108878418B (zh) * 2017-05-12 2021-02-09 中芯国际集成电路制造(上海)有限公司 半导体装置、检测器件发热的方法及制造方法
US10325824B2 (en) * 2017-06-13 2019-06-18 Globalfoundries Inc. Methods, apparatus and system for threshold voltage control in FinFET devices
CN108038274B (zh) * 2017-11-27 2021-08-20 深圳市兴森快捷电路科技股份有限公司 一种pcb与ic封装协同设计方法及装置

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289658A (ja) * 1985-06-18 1986-12-19 Fujitsu Ltd 半導体集積回路
EP0251682A3 (en) * 1986-06-25 1989-12-06 Hewlett-Packard Company Integrated bipolar-mos device
JPH02294063A (ja) 1989-05-08 1990-12-05 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5101257A (en) 1991-07-01 1992-03-31 Motorola, Inc. Semiconductor device having merged bipolar and MOS transistors and process for making the same
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
US5717241A (en) * 1993-12-09 1998-02-10 Northern Telecom Limited Gate controlled lateral bipolar junction transistor
US5498885A (en) * 1994-09-26 1996-03-12 Northern Telecom Limited Modulation circuit
JPH1027859A (ja) * 1996-07-09 1998-01-27 Yamaha Corp 複合半導体素子
US6191451B1 (en) * 1998-01-30 2001-02-20 International Business Machines Corporation Semiconductor device with decoupling capacitance
US6137142A (en) * 1998-02-24 2000-10-24 Sun Microsystems, Inc. MOS device structure and method for reducing PN junction leakage
JP3255147B2 (ja) * 1998-06-19 2002-02-12 株式会社デンソー 絶縁ゲート型トランジスタのサージ保護回路
US6429491B1 (en) * 1999-10-20 2002-08-06 Transmeta Corporation Electrostatic discharge protection for MOSFETs
US6693331B2 (en) * 1999-11-18 2004-02-17 Intel Corporation Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
JP3475237B2 (ja) * 2000-07-24 2003-12-08 東京大学長 電力制御装置及び方法並びに電力制御プログラムを記録した記録媒体
US6498357B2 (en) * 2001-02-09 2002-12-24 United Microelectronics Corp. Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process
JP4761644B2 (ja) * 2001-04-18 2011-08-31 三菱電機株式会社 半導体装置
KR100456526B1 (ko) * 2001-05-22 2004-11-09 삼성전자주식회사 식각저지막을 갖는 에스오아이 기판, 그 제조방법, 그위에 제작된 에스오아이 집적회로 및 그것을 사용하여에스오아이 집적회로를 제조하는 방법
US6770918B2 (en) * 2001-09-11 2004-08-03 Sarnoff Corporation Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies
KR100854077B1 (ko) * 2002-05-28 2008-08-25 페어차일드코리아반도체 주식회사 웨이퍼 본딩을 이용한 soi 기판 제조 방법과 이 soi기판을 사용한 상보형 고전압 바이폴라 트랜지스터 제조방법
US7173310B2 (en) 2002-12-03 2007-02-06 International Business Machines Corporation Lateral lubistor structure and method
EP1599904A4 (en) * 2002-12-03 2006-04-26 Ibm STRUCTURE AND METHOD FOR LATERAL LUBISTOR
US7582938B2 (en) * 2003-10-01 2009-09-01 Lsi Corporation I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
US6979869B2 (en) * 2003-10-01 2005-12-27 Lsi Logic Corporation Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process
US7095092B2 (en) * 2004-04-30 2006-08-22 Freescale Semiconductor, Inc. Semiconductor device and method of forming the same
TWI233688B (en) * 2004-08-30 2005-06-01 Ind Tech Res Inst Diode structure with low substrate leakage current and applications thereof
US20060131606A1 (en) * 2004-12-18 2006-06-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods
US7566914B2 (en) * 2005-07-07 2009-07-28 Intersil Americas Inc. Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits
US7468617B1 (en) * 2005-11-30 2008-12-23 Altera Corporation Electrostatic discharge (ESD) protection device for use with multiple I/O standards
ITMI20070353A1 (it) * 2007-02-23 2008-08-24 Univ Padova Transistore ad effetto di campo con giunzione metallo-semiconduttore.
TWI402594B (zh) * 2007-04-27 2013-07-21 Chunghwa Picture Tubes Ltd 主動元件陣列基板
US7808039B2 (en) 2008-04-09 2010-10-05 International Business Machines Corporation SOI transistor with merged lateral bipolar transistor
US8564079B2 (en) * 2008-04-21 2013-10-22 Qualcomm Incorporated STT MRAM magnetic tunnel junction architecture and integration
US8030151B2 (en) * 2009-03-27 2011-10-04 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
JP2012209339A (ja) * 2011-03-29 2012-10-25 Citizen Holdings Co Ltd フィン型電界効果トランジスタ
US8304838B1 (en) * 2011-08-23 2012-11-06 Amazing Microelectronics Corp. Electrostatic discharge protection device structure
TWI455274B (zh) * 2011-11-09 2014-10-01 威盛電子股份有限公司 靜電放電保護裝置
KR101207919B1 (ko) 2011-11-30 2012-12-04 숭실대학교산학협력단 결합형 트랜지스터 및 그 제조 방법
US20130270508A1 (en) * 2012-04-11 2013-10-17 Agency For Science, Technology And Research Non-Volatile Memory Device and Method of Forming the Same
US9019667B2 (en) * 2012-11-08 2015-04-28 Freescale Semiconductor Inc. Protection device and related fabrication methods
US9330961B2 (en) * 2013-09-23 2016-05-03 Freescale Semiconductor, Inc. Stacked protection devices and related fabrication methods
US10483257B2 (en) * 2014-02-18 2019-11-19 Nxp Usa, Inc. Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection

Similar Documents

Publication Publication Date Title
JP2017505530A5 (enExample)
Cho et al. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors
JP2017506032A5 (enExample)
JP2017192124A5 (enExample)
JP2015014795A5 (ja) 表示装置、表示モジュール、電子機器
JP6219521B2 (ja) デュアルモードトランジスタ
JP2013251040A5 (enExample)
CN108140613A (zh) 过饱和电流场效应晶体管和跨阻抗mos装置
JP2016522434A5 (enExample)
Bestelink et al. Compact source-gated transistor analog circuits for ubiquitous sensors
JP2012003251A5 (ja) 表示装置
US9568929B2 (en) Bandgap reference circuit with beta-compensation
Jang et al. Ambipolarity factor of tunneling field-effect transistors (TFETs)
JP2014515588A5 (enExample)
JP2018509685A5 (enExample)
JP2017188666A5 (ja) 半導体装置
GB2544929A8 (en) Low-temperature polycrystalline silicon semiconductor thin-film transistor-based GOA circuit
JP2018534806A5 (enExample)
TWI565239B (zh) 具有穿隧場效電晶體(tfets)電路實現多工器邏輯功能
JP2016535487A5 (enExample)
WO2016095693A1 (zh) 触摸装置的驱动电路、驱动方法、触摸装置和显示装置
CN105703761B (zh) 输入/输出驱动电路
JP2014116592A5 (enExample)
Hu et al. Band-to-band-tunneling leakage suppression for ultra-thin-body GeOI MOSFETs using transistor stacking
Kumar Split length FGMOS MOS cell: a new block for low voltage applications