JP2017162903A - 半導体パッケージ及び半導体パッケージの製造方法 - Google Patents
半導体パッケージ及び半導体パッケージの製造方法 Download PDFInfo
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- 229910045601 alloy Inorganic materials 0.000 description 2
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- 229910052797 bismuth Inorganic materials 0.000 description 2
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- 230000007797 corrosion Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
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Abstract
【解決手段】ダイパッドと、前記ダイパッドの周辺に配置された複数の外部接続端子と、前記ダイパッドの上面に配置され、前記複数の外部接続端子と電気的に接続された半導体チップと、前記ダイパッド、前記複数の外部接続端子及び前記半導体チップを埋設し、前記複数の外部接続端子の各々の外側端部を露出する封止材とを備え、前記複数の外部接続端子の各々は、前記外側端部の側面は第1領域を含み、前記第1領域にはめっきが施されていることを特徴とする半導体パッケージである。
【選択図】図1
Description
[半導体パッケージ100の構成]
本実施形態に係る半導体パッケージ100の構成について、図面を参照して詳細に説明する。
本実施形態に係る半導体パッケージ100の製造方法について、図面を参照して詳細に説明する。図5A乃至図5Iは、本実施形態に係る半導体パッケージ100の製造方法を説明する図である。これらの図において、図5A〜図5D、図5F、図5Hは、本実施形態に係る半導体パッケージ100の製造方法を説明する上面図及び断面図である。図5G及び図5Iはそれぞれ、図5F及び図5Hの状態における下面及び断面を拡大した図である。
[半導体パッケージ200の構成]
本実施形態に係る半導体パッケージ200の構成について、図面を参照して説明する。
本実施形態に係る半導体パッケージ200の製造方法について、図面を参照して詳細に説明する。図9A乃至図9Eは、本実施形態に係る半導体パッケージ200の製造方法を説明する図である。これらの図において、図9A〜図9Dは、本実施形態に係る半導体パッケージ200の製造方法を説明する上面図及び断面図である。図9Eは、図9Dの状態における下面及び断面を拡大した図である。
[半導体パッケージ300の構成]
本実施形態に係る半導体パッケージ300の構成について、図面を参照して説明する。
本実施形態に係る半導体パッケージ300の製造方法について、図面を参照して説明する。図12A乃至図12Eは、本実施形態に係る半導体パッケージ300の製造方法を説明する上面図及び断面図である。
100a:溝部
100b:第1開口部
102、202、302:リードフレーム
102a:上面
102b:下面
102c:側面
104:ダイパッド
104a:上面
104b:下面
104c:側面
106:第1連結部
108:第2連結部
110:第3連結部
114:外部接続端子
114a:上面
114b:下面
114c:側面
114d:内側端部
114e:外側端部
114f:第1領域
114g:凸部
114h:頂部
114i:テーパー部
116:半導体チップ
118:ワイヤ
120:封止材
120a:モールドライン
122:めっき
Claims (11)
- ダイパッドと、
前記ダイパッドの周辺に配置された複数の外部接続端子と、
前記ダイパッドの上面に配置され、前記複数の外部接続端子と電気的に接続された半導体チップと、
前記ダイパッド、前記複数の外部接続端子及び前記半導体チップを埋設し、前記複数の外部接続端子の各々の外側端部を露出する封止材とを備え、
前記複数の外部接続端子の各々は、前記外側端部の側面は第1領域を含み、前記第1領域にはめっきが施されていることを特徴とする半導体パッケージ。 - 前記第1領域は、前記外側端部の側面に等しいことを特徴とする請求項1に記載の半導体パッケージ。
- 前記複数の外部接続端子の各々は、前記外側端部の側面に凸部を有し、前記第1領域は、前記凸部の頂部を含むことを特徴とする請求項1に記載の半導体パッケージ。
- 前記複数の外部接続端子の各々は、前記外側端部の側面にテーパー部を有し、前記第1領域は、前記テーパー部を含むことを特徴とする請求項1に記載の半導体パッケージ。
- 複数の半導体パッケージに個片化される複数の領域を備え、前記複数の領域の各々は、ダイパッド、前記ダイパッドの周辺に配置された複数の外部接続端子、前記ダイパッドに連結され、前記複数の外部接続端子の外側端部を連結する第1連結部、及び前記複数の外部接続端子の内側端部を連結する第2連結部を含み、前記第2連結部は、上面から薄化されていることを特徴とするリードフレームを準備し、
前記リードフレームの上面の前記ダイパッド上に、前記複数の外部端子に電気的に接続された半導体チップを配置し、
前記ダイパッド、前記複数の外部接続端子及び前記半導体チップを埋設し、前記複数の外部接続端子の各々の外側端部を露出する封止材を形成し、
金型加工により、前記複数の外部接続端子及び前記第1連結部の連結部を除去する第1開口部を形成し、
前記リードフレームに電流を供給する電解めっき処理により、前記リードフレームの露出した領域にめっきを形成し、
前記リードフレームの下面から、前記複数の外部接続端子及び前記第2連結部を分離する溝部を形成し、
金型加工により、前記複数の半導体パッケージに個片化することを含む半導体パッケージの製造方法。 - 前記第1開口部は、矩形状であることを特徴とする請求項5に記載の半導体パッケージの製造方法。
- 複数の半導体パッケージに個片化される複数の領域を備え、前記複数の領域の各々は、ダイパッド、前記ダイパッドの周辺に配置された複数の外部接続端子、前記ダイパッドに連結され、前記複数の外部接続端子の外側端部を連結する第1連結部を含み、前記第1連結部は、前記複数の外部接続端子の外側端部に沿って配置された第1開口部を有することを特徴とするリードフレームを準備し、
前記リードフレームの上面の前記ダイパッドの上に、前記複数の外部端子に電気的に接続された半導体チップを配置し、
前記ダイパッド、前記複数の外部接続端子及び前記半導体チップを埋設し、前記複数の外部接続端子の各々の外側端部を露出する封止材を形成し、
前記リードフレームに電流を供給する電解めっき処理により、前記複数の外部接続端子の露出した領域にめっきを形成し、
金型加工により、前記複数の半導体パッケージに個片化すると共に、前記第1開口部の側壁の一部を側面に有する前記複数の外部接続端子の各々を形成することを含む半導体パッケージの製造方法。 - 前記第1開口部は、矩形状であることを特徴とする請求項7に記載の半導体パッケージの製造方法。
- ダイシングラインによって区画され、複数の半導体パッケージに個片化される複数の領域を備え、前記複数の領域の各々は、ダイパッド、前記ダイパッドの周辺に配置された複数の外部接続端子、前記ダイパッドに連結され、前記複数の外部接続端子の外側端部を連結する第1連結部を含むリードフレームを準備し、
前記リードフレームの上面の前記ダイパッドの上に、前記複数の外部端子に電気的に接続された半導体チップを配置し、
前記ダイパッド、前記複数の外部接続端子及び前記半導体チップを埋設し、前記複数の外部接続端子の各々の外側端部を露出する封止材を形成し、
切削加工により、前記複数の外部接続端子の各々の外側端部の下面の少なくとも一部を薄化し、
前記リードフレームに電流を供給する電解めっき処理により、前記複数の外部接続端子の露出した領域にめっきを形成し、
切削加工により、前記複数の半導体パッケージに個片化することを含む半導体パッケージの製造方法。 - 前記複数の外部接続端子の各々の外側端部の下面の少なくとも一部を薄化することは、底部の領域が前記ダイシングラインを含む溝部を形成することである請求項9に記載の半導体パッケージの製造方法。
- 前記溝部は、側壁に傾斜を有することを特徴とする請求項9に記載の半導体パッケージの製造方法。
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US10163766B2 (en) | 2016-11-21 | 2018-12-25 | Semiconductor Components Industries, Llc | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks |
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US11127661B2 (en) | 2018-06-13 | 2021-09-21 | Tongfu Microelectronics Co., Ltd. | Semiconductor chip package method and semiconductor chip package device |
CN110120376B (zh) * | 2019-04-30 | 2021-07-06 | 深圳市广和通无线股份有限公司 | 无针脚模块 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11191561A (ja) * | 1997-12-26 | 1999-07-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2002289756A (ja) * | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2004319996A (ja) * | 2003-04-02 | 2004-11-11 | Yamaha Corp | 半導体パッケージ、その製造方法、および、これに使用するリードフレーム |
JP2008112961A (ja) * | 2006-10-04 | 2008-05-15 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
JP4362163B2 (ja) * | 1999-04-06 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3878781B2 (ja) | 1999-12-27 | 2007-02-07 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3602453B2 (ja) * | 2000-08-31 | 2004-12-15 | Necエレクトロニクス株式会社 | 半導体装置 |
JP4308528B2 (ja) * | 2001-01-31 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP4243270B2 (ja) * | 2001-12-14 | 2009-03-25 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4173346B2 (ja) * | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4372508B2 (ja) * | 2003-10-06 | 2009-11-25 | ローム株式会社 | リードフレームの製造方法およびそれを用いた半導体装置の製造方法、ならびに半導体装置ならびにそれを備えた携帯機器および電子装置 |
JP3994095B2 (ja) * | 2004-06-23 | 2007-10-17 | ローム株式会社 | 面実装型電子部品 |
US7608916B2 (en) * | 2006-02-02 | 2009-10-27 | Texas Instruments Incorporated | Aluminum leadframes for semiconductor QFN/SON devices |
WO2008129601A1 (ja) * | 2007-04-05 | 2008-10-30 | Renesas Technology Corp. | 半導体装置の製造方法および半導体装置 |
CN104465414B (zh) * | 2009-07-06 | 2017-08-15 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
TWI431728B (zh) * | 2010-10-12 | 2014-03-21 | Powertech Technology Inc | 具強化式基座之半導體封裝構造 |
JP2012227445A (ja) * | 2011-04-21 | 2012-11-15 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP5824402B2 (ja) * | 2012-04-02 | 2015-11-25 | 株式会社巴川製紙所 | 半導体装置製造用マスクシート及びそれを用いた半導体装置の製造方法 |
JP2013225595A (ja) * | 2012-04-20 | 2013-10-31 | Shinko Electric Ind Co Ltd | リードフレーム及び半導体パッケージ並びにそれらの製造方法 |
JP2014007363A (ja) * | 2012-06-27 | 2014-01-16 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
US8890301B2 (en) * | 2012-08-01 | 2014-11-18 | Analog Devices, Inc. | Packaging and methods for packaging |
JP6121692B2 (ja) * | 2012-11-05 | 2017-04-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6125209B2 (ja) * | 2012-11-19 | 2017-05-10 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
JP6030970B2 (ja) * | 2013-02-12 | 2016-11-24 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP6370071B2 (ja) * | 2014-03-19 | 2018-08-08 | エイブリック株式会社 | 半導体装置及びその製造方法 |
WO2015145651A1 (ja) * | 2014-03-27 | 2015-10-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
US9773722B1 (en) * | 2014-05-07 | 2017-09-26 | UTAC Headquarters Pte. Ltd. | Semiconductor package with partial plating on contact side surfaces |
JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
DE102015000063A1 (de) * | 2015-01-12 | 2016-07-14 | Micronas Gmbh | IC-Gehäuse |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11191561A (ja) * | 1997-12-26 | 1999-07-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2002289756A (ja) * | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2004319996A (ja) * | 2003-04-02 | 2004-11-11 | Yamaha Corp | 半導体パッケージ、その製造方法、および、これに使用するリードフレーム |
JP2008112961A (ja) * | 2006-10-04 | 2008-05-15 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
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