JP2016519443A - 安定した高移動度のmotftおよび低温での製作 - Google Patents

安定した高移動度のmotftおよび低温での製作 Download PDF

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JP2016519443A
JP2016519443A JP2016515344A JP2016515344A JP2016519443A JP 2016519443 A JP2016519443 A JP 2016519443A JP 2016515344 A JP2016515344 A JP 2016515344A JP 2016515344 A JP2016515344 A JP 2016515344A JP 2016519443 A JP2016519443 A JP 2016519443A
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layer
amorphous
high mobility
metal oxide
depositing
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JP2016519443A5 (enExample
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シェ,チャン−ロン
ユ,ガン
フーン,ファット
ミュソッフ,ユルゲン
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CBRITE Inc
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CBRITE Inc
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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    • H01L21/02104Forming layers
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    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
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    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D64/693Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2016515344A 2013-05-24 2014-05-07 安定した高移動度のmotftおよび低温での製作 Pending JP2016519443A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/902,514 2013-05-24
US13/902,514 US9356156B2 (en) 2013-05-24 2013-05-24 Stable high mobility MOTFT and fabrication at low temperature
PCT/US2014/037191 WO2014189681A2 (en) 2013-05-24 2014-05-07 Stable high mobility motft and fabrication at low temperature

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JP2016519443A true JP2016519443A (ja) 2016-06-30
JP2016519443A5 JP2016519443A5 (enExample) 2017-12-07

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US (2) US9356156B2 (enExample)
EP (1) EP3005420A4 (enExample)
JP (1) JP2016519443A (enExample)
KR (1) KR20160012165A (enExample)
CN (1) CN105308753A (enExample)
WO (1) WO2014189681A2 (enExample)

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JP2017143135A (ja) * 2016-02-09 2017-08-17 株式会社ジャパンディスプレイ 薄膜トランジスタ
KR20200069472A (ko) * 2018-12-07 2020-06-17 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
WO2022249872A1 (ja) * 2021-05-26 2022-12-01 株式会社ニコン 半導体装置、電子デバイス、pHセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法

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US9362413B2 (en) * 2013-11-15 2016-06-07 Cbrite Inc. MOTFT with un-patterned etch-stop
US9136355B2 (en) * 2013-12-03 2015-09-15 Intermolecular, Inc. Methods for forming amorphous silicon thin film transistors
FR3024589B1 (fr) * 2014-07-29 2017-12-08 Commissariat Energie Atomique Dispositif electronique et son procede de fabrication
US20160313282A1 (en) * 2015-04-27 2016-10-27 Chan-Long Shieh Motft and array circuit for chemical/biochemical applications
US9515158B1 (en) 2015-10-20 2016-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with insertion layer and method for manufacturing the same
US9496415B1 (en) 2015-12-02 2016-11-15 International Business Machines Corporation Structure and process for overturned thin film device with self-aligned gate and S/D contacts
KR102640383B1 (ko) 2016-03-22 2024-02-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 상기 반도체 장치를 포함하는 표시 장치
WO2017208109A1 (en) 2016-06-03 2017-12-07 Semiconductor Energy Laboratory Co., Ltd. Sputtering target, oxide semiconductor, oxynitride semiconductor, and transistor
CN107749422A (zh) * 2017-09-21 2018-03-02 信利(惠州)智能显示有限公司 氧化物半导体薄膜晶体管
KR20250053970A (ko) 2018-03-12 2025-04-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 금속 산화물 및 금속 산화물을 포함한 트랜지스터
CN109638070B (zh) * 2018-12-12 2021-01-15 广州新视界光电科技有限公司 氧化物半导体材料、薄膜晶体管及制备方法和显示面板

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JP2013041944A (ja) * 2011-08-12 2013-02-28 Fujifilm Corp 薄膜トランジスタ及びその製造方法、表示装置、イメージセンサー、x線センサー並びにx線デジタル撮影装置

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JP2017143135A (ja) * 2016-02-09 2017-08-17 株式会社ジャパンディスプレイ 薄膜トランジスタ
KR20200069472A (ko) * 2018-12-07 2020-06-17 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
KR102163565B1 (ko) * 2018-12-07 2020-10-12 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
WO2022249872A1 (ja) * 2021-05-26 2022-12-01 株式会社ニコン 半導体装置、電子デバイス、pHセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法
JP7632606B2 (ja) 2021-05-26 2025-02-19 株式会社ニコン 半導体装置、電子デバイス、pHセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法

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