JP2015505171A5 - - Google Patents
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- Publication number
- JP2015505171A5 JP2015505171A5 JP2014552358A JP2014552358A JP2015505171A5 JP 2015505171 A5 JP2015505171 A5 JP 2015505171A5 JP 2014552358 A JP2014552358 A JP 2014552358A JP 2014552358 A JP2014552358 A JP 2014552358A JP 2015505171 A5 JP2015505171 A5 JP 2015505171A5
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- tapered portion
- insulating layer
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims 16
- 239000004065 semiconductor Substances 0.000 claims 15
- 239000004020 conductor Substances 0.000 claims 6
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261586463P | 2012-01-13 | 2012-01-13 | |
| US61/586,463 | 2012-01-13 | ||
| US201261671607P | 2012-07-13 | 2012-07-13 | |
| US61/671,607 | 2012-07-13 | ||
| US13/724,038 | 2012-12-21 | ||
| US13/724,038 US8975729B2 (en) | 2012-01-13 | 2012-12-21 | Integrating through substrate vias into middle-of-line layers of integrated circuits |
| PCT/US2013/021342 WO2013106796A1 (en) | 2012-01-13 | 2013-01-12 | Integrating through substrate vias into middle-of-line layers of integrated circuits |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015505171A JP2015505171A (ja) | 2015-02-16 |
| JP2015505171A5 true JP2015505171A5 (enExample) | 2015-06-18 |
| JP6012763B2 JP6012763B2 (ja) | 2016-10-25 |
Family
ID=48779411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014552358A Active JP6012763B2 (ja) | 2012-01-13 | 2013-01-12 | 基板貫通ビアを集積回路の中間工程層に組み込むこと |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8975729B2 (enExample) |
| EP (2) | EP3731265B1 (enExample) |
| JP (1) | JP6012763B2 (enExample) |
| KR (1) | KR101548664B1 (enExample) |
| CN (1) | CN104067383B (enExample) |
| ES (1) | ES2829898T3 (enExample) |
| WO (1) | WO2013106796A1 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245790B2 (en) * | 2013-01-23 | 2016-01-26 | GlobalFoundries, Inc. | Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via |
| CN104637861A (zh) * | 2013-11-11 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | 硅通孔工艺方法 |
| US20160079167A1 (en) * | 2014-09-12 | 2016-03-17 | Qualcomm Incorporated | Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods |
| US9620454B2 (en) | 2014-09-12 | 2017-04-11 | Qualcomm Incorporated | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods |
| US9653399B2 (en) * | 2015-02-13 | 2017-05-16 | Qualcomm Incorporated | Middle-of-line integration methods and semiconductor devices |
| KR102411064B1 (ko) * | 2015-03-10 | 2022-06-21 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그의 제조방법 |
| KR102366804B1 (ko) | 2015-05-13 | 2022-02-25 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US10748906B2 (en) | 2015-05-13 | 2020-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US9728501B2 (en) * | 2015-12-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
| US9761509B2 (en) | 2015-12-29 | 2017-09-12 | United Microelectronics Corp. | Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device |
| KR102495587B1 (ko) | 2016-01-12 | 2023-02-03 | 삼성전자주식회사 | 관통 비아 구조체를 갖는 반도체 소자 |
| US10199315B2 (en) * | 2016-08-29 | 2019-02-05 | Globalfoundries Inc. | Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects |
| US10049981B2 (en) * | 2016-09-08 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Through via structure, semiconductor device and manufacturing method thereof |
| US9768133B1 (en) | 2016-09-22 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
| KR102406583B1 (ko) | 2017-07-12 | 2022-06-09 | 삼성전자주식회사 | 반도체 장치 |
| CN107958194B (zh) * | 2017-08-17 | 2021-11-19 | 柳州梓博科技有限公司 | 光电传感装置及电子设备 |
| CN113228240B (zh) * | 2018-10-31 | 2024-08-09 | 浜松光子学株式会社 | 镶嵌配线构造、致动装置、和镶嵌配线构造的制造方法 |
| JP7506604B2 (ja) | 2018-10-31 | 2024-06-26 | 浜松ホトニクス株式会社 | 半導体基板の製造方法、ダマシン配線構造の製造方法、半導体基板、及びダマシン配線構造 |
| US11495559B2 (en) * | 2020-04-27 | 2022-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits |
| US11355464B2 (en) * | 2020-11-10 | 2022-06-07 | Nanya Technology Corporation | Semiconductor device structure with bottle-shaped through silicon via and method for forming the same |
| KR102856349B1 (ko) | 2021-04-16 | 2025-09-04 | 삼성전자주식회사 | 반도체 칩 및 이를 포함하는 반도체 패키지 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545581A (en) | 1994-12-06 | 1996-08-13 | International Business Machines Corporation | Plug strap process utilizing selective nitride and oxide etches |
| EP0926726A1 (en) | 1997-12-16 | 1999-06-30 | STMicroelectronics S.r.l. | Fabrication process and electronic device having front-back through contacts for bonding onto boards |
| JP4322508B2 (ja) | 2003-01-15 | 2009-09-02 | 新光電気工業株式会社 | 半導体装置の製造方法 |
| JP4878434B2 (ja) * | 2004-09-22 | 2012-02-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7892972B2 (en) | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
| US7564115B2 (en) * | 2007-05-16 | 2009-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tapered through-silicon via structure |
| US7615480B2 (en) | 2007-06-20 | 2009-11-10 | Lam Research Corporation | Methods of post-contact back end of the line through-hole via integration |
| EP2306506B1 (en) | 2009-10-01 | 2013-07-31 | ams AG | Method of producing a semiconductor device having a through-wafer interconnect |
| JP5537197B2 (ja) | 2010-03-12 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US8405222B2 (en) | 2010-06-28 | 2013-03-26 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system with via and method of manufacture thereof |
-
2012
- 2012-12-21 US US13/724,038 patent/US8975729B2/en active Active
-
2013
- 2013-01-12 JP JP2014552358A patent/JP6012763B2/ja active Active
- 2013-01-12 WO PCT/US2013/021342 patent/WO2013106796A1/en not_active Ceased
- 2013-01-12 EP EP20179789.1A patent/EP3731265B1/en active Active
- 2013-01-12 EP EP13703655.4A patent/EP2803081B1/en active Active
- 2013-01-12 KR KR1020147022299A patent/KR101548664B1/ko active Active
- 2013-01-12 CN CN201380005315.9A patent/CN104067383B/zh active Active
- 2013-01-12 ES ES13703655T patent/ES2829898T3/es active Active
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