JP6012763B2 - 基板貫通ビアを集積回路の中間工程層に組み込むこと - Google Patents

基板貫通ビアを集積回路の中間工程層に組み込むこと Download PDF

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JP6012763B2
JP6012763B2 JP2014552358A JP2014552358A JP6012763B2 JP 6012763 B2 JP6012763 B2 JP 6012763B2 JP 2014552358 A JP2014552358 A JP 2014552358A JP 2014552358 A JP2014552358 A JP 2014552358A JP 6012763 B2 JP6012763 B2 JP 6012763B2
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substrate
layer
insulating layer
tsv
semiconductor wafer
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Japanese (ja)
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JP2015505171A5 (enExample
JP2015505171A (ja
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ヴィディヤ・ラマチャンドラ
シーチュン・グ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2014552358A 2012-01-13 2013-01-12 基板貫通ビアを集積回路の中間工程層に組み込むこと Active JP6012763B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201261586463P 2012-01-13 2012-01-13
US61/586,463 2012-01-13
US201261671607P 2012-07-13 2012-07-13
US61/671,607 2012-07-13
US13/724,038 2012-12-21
US13/724,038 US8975729B2 (en) 2012-01-13 2012-12-21 Integrating through substrate vias into middle-of-line layers of integrated circuits
PCT/US2013/021342 WO2013106796A1 (en) 2012-01-13 2013-01-12 Integrating through substrate vias into middle-of-line layers of integrated circuits

Publications (3)

Publication Number Publication Date
JP2015505171A JP2015505171A (ja) 2015-02-16
JP2015505171A5 JP2015505171A5 (enExample) 2015-06-18
JP6012763B2 true JP6012763B2 (ja) 2016-10-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014552358A Active JP6012763B2 (ja) 2012-01-13 2013-01-12 基板貫通ビアを集積回路の中間工程層に組み込むこと

Country Status (7)

Country Link
US (1) US8975729B2 (enExample)
EP (2) EP2803081B1 (enExample)
JP (1) JP6012763B2 (enExample)
KR (1) KR101548664B1 (enExample)
CN (1) CN104067383B (enExample)
ES (1) ES2829898T3 (enExample)
WO (1) WO2013106796A1 (enExample)

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US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
CN104637861A (zh) * 2013-11-11 2015-05-20 上海华虹宏力半导体制造有限公司 硅通孔工艺方法
US9620454B2 (en) * 2014-09-12 2017-04-11 Qualcomm Incorporated Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
US20160079167A1 (en) * 2014-09-12 2016-03-17 Qualcomm Incorporated Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods
US9653399B2 (en) 2015-02-13 2017-05-16 Qualcomm Incorporated Middle-of-line integration methods and semiconductor devices
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
KR102366804B1 (ko) 2015-05-13 2022-02-25 삼성전자주식회사 반도체 소자의 제조 방법
US10748906B2 (en) 2015-05-13 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9728501B2 (en) * 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
US9761509B2 (en) * 2015-12-29 2017-09-12 United Microelectronics Corp. Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
KR102495587B1 (ko) 2016-01-12 2023-02-03 삼성전자주식회사 관통 비아 구조체를 갖는 반도체 소자
US10199315B2 (en) * 2016-08-29 2019-02-05 Globalfoundries Inc. Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects
US10049981B2 (en) * 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US9768133B1 (en) 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
KR102406583B1 (ko) 2017-07-12 2022-06-09 삼성전자주식회사 반도체 장치
CN107958194B (zh) * 2017-08-17 2021-11-19 柳州梓博科技有限公司 光电传感装置及电子设备
EP3876266A4 (en) 2018-10-31 2022-08-17 Hamamatsu Photonics K.K. METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DAMASZEN WIRING STRUCTURE, SEMICONDUCTOR SUBSTRATE AND DAMASZEN WIRING STRUCTURE
CN118908143A (zh) * 2018-10-31 2024-11-08 浜松光子学株式会社 镶嵌配线构造、致动装置、和镶嵌配线构造的制造方法
US11495559B2 (en) * 2020-04-27 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits
US11355464B2 (en) * 2020-11-10 2022-06-07 Nanya Technology Corporation Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
KR102856349B1 (ko) 2021-04-16 2025-09-04 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지

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US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
EP0926726A1 (en) 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
JP4322508B2 (ja) 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
JP4878434B2 (ja) * 2004-09-22 2012-02-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7892972B2 (en) 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US7564115B2 (en) * 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7615480B2 (en) 2007-06-20 2009-11-10 Lam Research Corporation Methods of post-contact back end of the line through-hole via integration
EP2306506B1 (en) 2009-10-01 2013-07-31 ams AG Method of producing a semiconductor device having a through-wafer interconnect
JP5537197B2 (ja) 2010-03-12 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8405222B2 (en) 2010-06-28 2013-03-26 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with via and method of manufacture thereof

Also Published As

Publication number Publication date
US20130181330A1 (en) 2013-07-18
KR20140117521A (ko) 2014-10-07
WO2013106796A1 (en) 2013-07-18
US8975729B2 (en) 2015-03-10
CN104067383A (zh) 2014-09-24
EP3731265B1 (en) 2023-03-08
EP2803081A1 (en) 2014-11-19
ES2829898T3 (es) 2021-06-02
JP2015505171A (ja) 2015-02-16
EP2803081B1 (en) 2020-08-12
EP3731265A1 (en) 2020-10-28
KR101548664B1 (ko) 2015-09-01
CN104067383B (zh) 2017-04-12

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