KR101548664B1 - 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 - Google Patents

집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 Download PDF

Info

Publication number
KR101548664B1
KR101548664B1 KR1020147022299A KR20147022299A KR101548664B1 KR 101548664 B1 KR101548664 B1 KR 101548664B1 KR 1020147022299 A KR1020147022299 A KR 1020147022299A KR 20147022299 A KR20147022299 A KR 20147022299A KR 101548664 B1 KR101548664 B1 KR 101548664B1
Authority
KR
South Korea
Prior art keywords
substrate
layer
isolation layer
semiconductor device
tsv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147022299A
Other languages
English (en)
Korean (ko)
Other versions
KR20140117521A (ko
Inventor
비드야 라마찬드라
시쿤 구
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20140117521A publication Critical patent/KR20140117521A/ko
Application granted granted Critical
Publication of KR101548664B1 publication Critical patent/KR101548664B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
KR1020147022299A 2012-01-13 2013-01-12 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 Active KR101548664B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201261586463P 2012-01-13 2012-01-13
US61/586,463 2012-01-13
US201261671607P 2012-07-13 2012-07-13
US61/671,607 2012-07-13
US13/724,038 2012-12-21
US13/724,038 US8975729B2 (en) 2012-01-13 2012-12-21 Integrating through substrate vias into middle-of-line layers of integrated circuits
PCT/US2013/021342 WO2013106796A1 (en) 2012-01-13 2013-01-12 Integrating through substrate vias into middle-of-line layers of integrated circuits

Publications (2)

Publication Number Publication Date
KR20140117521A KR20140117521A (ko) 2014-10-07
KR101548664B1 true KR101548664B1 (ko) 2015-09-01

Family

ID=48779411

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147022299A Active KR101548664B1 (ko) 2012-01-13 2013-01-12 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스

Country Status (7)

Country Link
US (1) US8975729B2 (enExample)
EP (2) EP2803081B1 (enExample)
JP (1) JP6012763B2 (enExample)
KR (1) KR101548664B1 (enExample)
CN (1) CN104067383B (enExample)
ES (1) ES2829898T3 (enExample)
WO (1) WO2013106796A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
CN104637861A (zh) * 2013-11-11 2015-05-20 上海华虹宏力半导体制造有限公司 硅通孔工艺方法
US9620454B2 (en) * 2014-09-12 2017-04-11 Qualcomm Incorporated Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
US20160079167A1 (en) * 2014-09-12 2016-03-17 Qualcomm Incorporated Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods
US9653399B2 (en) 2015-02-13 2017-05-16 Qualcomm Incorporated Middle-of-line integration methods and semiconductor devices
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
KR102366804B1 (ko) 2015-05-13 2022-02-25 삼성전자주식회사 반도체 소자의 제조 방법
US10748906B2 (en) 2015-05-13 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9728501B2 (en) * 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
US9761509B2 (en) * 2015-12-29 2017-09-12 United Microelectronics Corp. Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
KR102495587B1 (ko) 2016-01-12 2023-02-03 삼성전자주식회사 관통 비아 구조체를 갖는 반도체 소자
US10199315B2 (en) * 2016-08-29 2019-02-05 Globalfoundries Inc. Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects
US10049981B2 (en) * 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US9768133B1 (en) 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
KR102406583B1 (ko) 2017-07-12 2022-06-09 삼성전자주식회사 반도체 장치
CN107958194B (zh) * 2017-08-17 2021-11-19 柳州梓博科技有限公司 光电传感装置及电子设备
EP3876266A4 (en) 2018-10-31 2022-08-17 Hamamatsu Photonics K.K. METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DAMASZEN WIRING STRUCTURE, SEMICONDUCTOR SUBSTRATE AND DAMASZEN WIRING STRUCTURE
CN118908143A (zh) * 2018-10-31 2024-11-08 浜松光子学株式会社 镶嵌配线构造、致动装置、和镶嵌配线构造的制造方法
US11495559B2 (en) * 2020-04-27 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits
US11355464B2 (en) * 2020-11-10 2022-06-07 Nanya Technology Corporation Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
KR102856349B1 (ko) 2021-04-16 2025-09-04 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US7473630B2 (en) 2004-09-22 2009-01-06 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090269905A1 (en) 2007-05-16 2009-10-29 Chen-Shien Chen Tapered Through-Silicon Via Structure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926726A1 (en) 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
JP4322508B2 (ja) 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
US7892972B2 (en) 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US7615480B2 (en) 2007-06-20 2009-11-10 Lam Research Corporation Methods of post-contact back end of the line through-hole via integration
EP2306506B1 (en) 2009-10-01 2013-07-31 ams AG Method of producing a semiconductor device having a through-wafer interconnect
JP5537197B2 (ja) 2010-03-12 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8405222B2 (en) 2010-06-28 2013-03-26 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with via and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US7473630B2 (en) 2004-09-22 2009-01-06 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090269905A1 (en) 2007-05-16 2009-10-29 Chen-Shien Chen Tapered Through-Silicon Via Structure
US7816227B2 (en) 2007-05-16 2010-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure

Also Published As

Publication number Publication date
US20130181330A1 (en) 2013-07-18
KR20140117521A (ko) 2014-10-07
JP6012763B2 (ja) 2016-10-25
WO2013106796A1 (en) 2013-07-18
US8975729B2 (en) 2015-03-10
CN104067383A (zh) 2014-09-24
EP3731265B1 (en) 2023-03-08
EP2803081A1 (en) 2014-11-19
ES2829898T3 (es) 2021-06-02
JP2015505171A (ja) 2015-02-16
EP2803081B1 (en) 2020-08-12
EP3731265A1 (en) 2020-10-28
CN104067383B (zh) 2017-04-12

Similar Documents

Publication Publication Date Title
KR101548664B1 (ko) 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스
KR101580941B1 (ko) 스트레인-완화된 tsv에 대한 구조 및 방법
KR101610323B1 (ko) 저-ｋ 배선 층을 관통하여 기판 관통 비아들을 패터닝하기 위한 저-ｋ 유전체 보호 스페이서를 형성하는 방법 및 상기 방법에 의해 형성된 스페이서를 포함하는 반도체 다이
KR101654794B1 (ko) 집적 회로들의 웨이퍼 후면 층들로부터 기판 관통 비아들의 통합
US9142490B2 (en) Integrated circuit device having through-silicon-via structure and method of manufacturing the integrated circuit device
US20100164062A1 (en) Method of manufacturing through-silicon-via and through-silicon-via structure
US9666660B2 (en) Semiconductor structures including metal insulator metal capacitor

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20140808

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
A302 Request for accelerated examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20150409

Comment text: Request for Examination of Application

PA0302 Request for accelerated examination

Patent event date: 20150409

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20150417

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20150821

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20150825

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20150826

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
FPAY Annual fee payment

Payment date: 20180628

Year of fee payment: 4

PR1001 Payment of annual fee

Payment date: 20180628

Start annual number: 4

End annual number: 4

FPAY Annual fee payment

Payment date: 20190624

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20190624

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20200624

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20230626

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20240624

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20250625

Start annual number: 11

End annual number: 11