JP2018523919A5 - - Google Patents
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- Publication number
- JP2018523919A5 JP2018523919A5 JP2018503557A JP2018503557A JP2018523919A5 JP 2018523919 A5 JP2018523919 A5 JP 2018523919A5 JP 2018503557 A JP2018503557 A JP 2018503557A JP 2018503557 A JP2018503557 A JP 2018503557A JP 2018523919 A5 JP2018523919 A5 JP 2018523919A5
- Authority
- JP
- Japan
- Prior art keywords
- die
- conductive path
- layer
- pid
- pop structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 claims 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/812,476 US9401350B1 (en) | 2015-07-29 | 2015-07-29 | Package-on-package (POP) structure including multiple dies |
| US14/812,476 | 2015-07-29 | ||
| PCT/US2016/044487 WO2017019866A1 (en) | 2015-07-29 | 2016-07-28 | Package-on-package (pop) structure including multiple dies |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018523919A JP2018523919A (ja) | 2018-08-23 |
| JP2018523919A5 true JP2018523919A5 (enExample) | 2019-08-15 |
| JP6914245B2 JP6914245B2 (ja) | 2021-08-04 |
Family
ID=56411293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018503557A Active JP6914245B2 (ja) | 2015-07-29 | 2016-07-28 | 複数のダイを含むパッケージオンパッケージ（ｐｏｐ）構造 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9401350B1 (enExample) |
| EP (2) | EP3329512A1 (enExample) |
| JP (1) | JP6914245B2 (enExample) |
| KR (1) | KR102546223B1 (enExample) |
| CN (1) | CN107851588B (enExample) |
| BR (1) | BR112018001783B8 (enExample) |
| CA (1) | CA2990470A1 (enExample) |
| WO (1) | WO2017019866A1 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3465751B1 (en) * | 2016-06-03 | 2021-08-18 | Intel Corporation | Wireless module with antenna package and cap package |
| US9837341B1 (en) | 2016-09-15 | 2017-12-05 | Intel Corporation | Tin-zinc microbump structures |
| US11574874B2 (en) * | 2017-03-30 | 2023-02-07 | Intel Corporation | Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch |
| US11114599B2 (en) * | 2017-03-31 | 2021-09-07 | 3M Innovative Properties Company | Electronic devices including solid semiconductor dies |
| WO2020020825A1 (en) | 2018-07-23 | 2020-01-30 | Borealis Ag | Multilayer polypropylene film |
| US10665572B2 (en) * | 2018-08-15 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
| US20200083154A1 (en) | 2018-09-10 | 2020-03-12 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation |
| WO2020103147A1 (zh) * | 2018-11-23 | 2020-05-28 | 北京比特大陆科技有限公司 | 芯片散热结构、芯片结构、电路板和超算设备 |
| EP3723459A1 (en) | 2019-04-10 | 2020-10-14 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with high passive intermodulation (pim) performance |
| US11752743B2 (en) | 2019-06-05 | 2023-09-12 | Borealis Ag | Multilayer polypropylene film |
| KR102764370B1 (ko) | 2019-12-26 | 2025-02-07 | 삼성전자주식회사 | 반도체 패키지 |
| CN112867243A (zh) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | 多层电路板 |
| US20240222142A1 (en) * | 2022-12-28 | 2024-07-04 | Applied Materials, Inc. | Efficient autocatalytic metallization of polymeric surfaces |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798909A (en) | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
| US6437433B1 (en) | 2000-03-24 | 2002-08-20 | Andrew C. Ross | CSP stacking technology using rigid/flex construction |
| US6404043B1 (en) | 2000-06-21 | 2002-06-11 | Dense-Pac Microsystems, Inc. | Panel stacking of BGA devices to form three-dimensional modules |
| US7122904B2 (en) * | 2002-04-25 | 2006-10-17 | Macronix International Co., Ltd. | Semiconductor packaging device and manufacture thereof |
| US7388294B2 (en) | 2003-01-27 | 2008-06-17 | Micron Technology, Inc. | Semiconductor components having stacked dice |
| US20090008792A1 (en) * | 2004-11-19 | 2009-01-08 | Industrial Technology Research Institute | Three-dimensional chip-stack package and active component on a substrate |
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| US20110024890A1 (en) * | 2007-06-29 | 2011-02-03 | Stats Chippac, Ltd. | Stackable Package By Using Internal Stacking Modules |
| TWI338941B (en) * | 2007-08-22 | 2011-03-11 | Unimicron Technology Corp | Semiconductor package structure |
| JP5310103B2 (ja) * | 2009-03-03 | 2013-10-09 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP5471605B2 (ja) * | 2009-03-04 | 2014-04-16 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US8558374B2 (en) | 2011-02-08 | 2013-10-15 | Endicott Interconnect Technologies, Inc. | Electronic package with thermal interposer and method of making same |
| US8883561B2 (en) * | 2011-04-30 | 2014-11-11 | Stats Chippac, Ltd. | Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP |
| US20130186676A1 (en) * | 2012-01-20 | 2013-07-25 | Futurewei Technologies, Inc. | Methods and Apparatus for a Substrate Core Layer |
| US9881894B2 (en) * | 2012-03-08 | 2018-01-30 | STATS ChipPAC Pte. Ltd. | Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration |
| CN202871783U (zh) * | 2012-08-31 | 2013-04-10 | 江阴长电先进封装有限公司 | 一种芯片嵌入式堆叠圆片级封装结构 |
| US20140246781A1 (en) * | 2013-03-04 | 2014-09-04 | Kabushiki Kaisha Toshiba | Semiconductor device, method of forming a packaged chip device and chip package |
| US9455218B2 (en) * | 2013-03-28 | 2016-09-27 | Intel Corporation | Embedded die-down package-on-package device |
| KR102065008B1 (ko) * | 2013-09-27 | 2020-01-10 | 삼성전자주식회사 | 적층형 반도체 패키지 |
| US20150255411A1 (en) * | 2014-03-05 | 2015-09-10 | Omkar G. Karhade | Die-to-die bonding and associated package configurations |
-
2015
- 2015-07-29 US US14/812,476 patent/US9401350B1/en active Active
-
2016
- 2016-07-28 JP JP2018503557A patent/JP6914245B2/ja active Active
- 2016-07-28 WO PCT/US2016/044487 patent/WO2017019866A1/en not_active Ceased
- 2016-07-28 BR BR112018001783A patent/BR112018001783B8/pt active IP Right Grant
- 2016-07-28 CN CN201680044487.0A patent/CN107851588B/zh active Active
- 2016-07-28 KR KR1020187002486A patent/KR102546223B1/ko active Active
- 2016-07-28 EP EP16751411.6A patent/EP3329512A1/en not_active Ceased
- 2016-07-28 EP EP24194383.6A patent/EP4439634A3/en active Pending
- 2016-07-28 CA CA2990470A patent/CA2990470A1/en active Pending
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